diff options
| author | Andrew Jeffery <andrew@aj.id.au> | 2019-07-11 07:19:42 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-08-05 13:41:18 +0300 |
| commit | 2eda1cdec49f8ae7878e60d1b06bd8157a95424f (patch) | |
| tree | 37e7778f68b8f7ad4e697fe9f6dd01195574d34e /drivers/pinctrl/aspeed/Kconfig | |
| parent | 86392fac9a9c92f36c0a422a3075865a0fe959f9 (diff) | |
| download | linux-2eda1cdec49f8ae7878e60d1b06bd8157a95424f.tar.xz | |
pinctrl: aspeed: Add AST2600 pinmux support
The AST2600 pinmux is fairly similar to the previous generations of
ASPEED BMC SoCs in terms of architecture, though differ in some of the
design details. The complexity of the pin expressions is largely reduced
(e.g. there are no-longer signals with multiple expressions muxing them
to the associated pin), and there are now signals and buses with
multiple pin groups.
The driver implements pinmux support for all 244 GPIO-capable pins plus
a further four pins that are not GPIO capable but which expose multiple
signals. pinconf will be implemented in a follow-up patch.
The implementation has been smoke-tested under qemu, and run on hardware
by ASPEED.
Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed/Kconfig')
| -rw-r--r-- | drivers/pinctrl/aspeed/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 4cf54172f8fb..de8b185c4fee 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -23,3 +23,11 @@ config PINCTRL_ASPEED_G5 help Say Y here to enable pin controller support for Aspeed's 5th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G6 + bool "Aspeed G6 SoC pin control" + depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 6th + generation SoCs. GPIO is provided by a separate GPIO driver. |