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author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-08-31 00:38:37 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-08-31 00:38:37 +0300 |
commit | 7d6e3fa87e732ec1e7761bf325c0907685c8571b (patch) | |
tree | ff5c3983e6e8ebf277a95dfa41d63ad3fef65db0 /drivers/pinctrl/intel/pinctrl-baytrail.c | |
parent | e5e726f7bb9f711102edea7e5bd511835640e3b4 (diff) | |
parent | 47fb0cfdb7a71a8a0ff8fe1d117363dc81f6ca77 (diff) | |
download | linux-7d6e3fa87e732ec1e7761bf325c0907685c8571b.tar.xz |
Merge tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"Updates to the interrupt core and driver subsystems:
Core changes:
- The usual set of small fixes and improvements all over the place,
but nothing stands out
MSI changes:
- Further consolidation of the PCI/MSI interrupt chip code
- Make MSI sysfs code independent of PCI/MSI and expose the MSI
interrupts of platform devices in the same way as PCI exposes them.
Driver changes:
- Support for ARM GICv3 EPPI partitions
- Treewide conversion to generic_handle_domain_irq() for all chained
interrupt controllers
- Conversion to bitmap_zalloc() throughout the irq chip drivers
- The usual set of small fixes and improvements"
* tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (57 commits)
platform-msi: Add ABI to show msi_irqs of platform devices
genirq/msi: Move MSI sysfs handling from PCI to MSI core
genirq/cpuhotplug: Demote debug printk to KERN_DEBUG
irqchip/qcom-pdc: Trim unused levels of the interrupt hierarchy
irqdomain: Export irq_domain_disconnect_hierarchy()
irqchip/gic-v3: Fix priority comparison when non-secure priorities are used
irqchip/apple-aic: Fix irq_disable from within irq handlers
pinctrl/rockchip: drop the gpio related codes
gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type
gpio/rockchip: support next version gpio controller
gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
gpio/rockchip: add driver for rockchip gpio
dt-bindings: gpio: change items restriction of clock for rockchip,gpio-bank
pinctrl/rockchip: add pinctrl device to gpio bank struct
pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
pinctrl/rockchip: always enable clock for gpio controller
genirq: Fix kernel doc indentation
EDAC/altera: Convert to generic_handle_domain_irq()
powerpc: Bulk conversion to generic_handle_domain_irq()
nios2: Bulk conversion to generic_handle_domain_irq()
...
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-baytrail.c')
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-baytrail.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 394a421a19d5..8f23d126c6a7 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1444,7 +1444,6 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) u32 base, pin; void __iomem *reg; unsigned long pending; - unsigned int virq; /* check from GPIO controller which pin triggered the interrupt */ for (base = 0; base < vg->chip.ngpio; base += 32) { @@ -1460,10 +1459,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) raw_spin_lock(&byt_lock); pending = readl(reg); raw_spin_unlock(&byt_lock); - for_each_set_bit(pin, &pending, 32) { - virq = irq_find_mapping(vg->chip.irq.domain, base + pin); - generic_handle_irq(virq); - } + for_each_set_bit(pin, &pending, 32) + generic_handle_domain_irq(vg->chip.irq.domain, base + pin); } chip->irq_eoi(data); } |