diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-05-03 01:40:41 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-05-03 01:40:41 +0300 |
| commit | 348551ddaf311c76b01cdcbaf61b6fef06a49144 (patch) | |
| tree | 65f217523ea41fac639a6a51ac56865dadbdd26d /drivers/pinctrl/renesas | |
| parent | 7df047b3f0aa0c0ba730b6be9ab35c0053a3d4fd (diff) | |
| parent | b7badd752de05312fdb1aeb388480f706d0c087f (diff) | |
| download | linux-348551ddaf311c76b01cdcbaf61b6fef06a49144.tar.xz | |
Merge tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Mostly drivers! Nothing special: some new Qualcomm chips as usual, and
the new NXP S32 and nVidia BlueField-3.
Core changes:
- Make a lot of pin controllers with GPIO and irqchips immutable,
i.e. not living structs, but const structs. This is driving a
changed initiated by the irqchip maintainers.
New drivers:
- New driver for the NXP S32 SoC pin controller
- As part of a thorough cleanup and restructuring of the
Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were
folded into the Mediatek directory and the family is renamed
"mtmips". The Ralink chips live on as Mediatek MIPS family where
new variants can be added. As part of this work also the device
tree bindings were reworked.
- New subdriver for the Qualcomm SM7150 SoC.
- New subdriver for the Qualcomm IPQ9574 SoC.
- New driver for the nVidia BlueField-3 SoC.
- Support for the Qualcomm PMM8654AU mixed signal circuit GPIO.
- Support for the Qualcomm PMI632 mixed signal circuit GPIO.
Improvements:
- Add some missing pins and generic cleanups on the Renesas r8a779g0
and r8a779g0 pin controllers. Generic Renesas extension for power
source selection on several SoCs.
- Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers
- Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver.
- Several device tree binding cleanups as the binding YAML syntax is
solidifying"
* tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
pinctrl-bcm2835.c: fix race condition when setting gpio dir
dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2"
dt-bindings: pinctrl: qcom: Add few missing functions
pinctrl: qcom: spmi-gpio: Add PMI632 support
dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632
pinctrl: wpcm450: select MFD_SYSCON
pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip
pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip
pinctrl: qcom spmi-mpp: Convert to immutable irq_chip
pinctrl: plgpio: Convert to immutable irq_chip
pinctrl: pistachio: Convert to immutable irq_chip
pinctrl: pic32: Convert to immutable irq_chip
pinctrl: sx150x: Convert to immutable irq_chip
pinctrl: stmfx: Convert to immutable irq_chip
pinctrl: st: Convert to immutable irq_chip
pinctrl: mcp23s08: Convert to immutable irq_chip
pinctrl: equilibrium: Convert to immutable irq_chip
pinctrl: npcm7xx: Convert to immutable irq_chip
pinctrl: armada-37xx: Convert to immutable irq_chip
pinctrl: nsp: Convert to immutable irq_chip
...
Diffstat (limited to 'drivers/pinctrl/renesas')
41 files changed, 1290 insertions, 6738 deletions
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 0903a0a41831..77730dc548ed 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -27,7 +27,6 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A7792 if ARCH_R8A7792 select PINCTRL_PFC_R8A7793 if ARCH_R8A7793 select PINCTRL_PFC_R8A7794 if ARCH_R8A7794 - select PINCTRL_PFC_R8A77950 if ARCH_R8A77950 select PINCTRL_PFC_R8A77951 if ARCH_R8A77951 select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 select PINCTRL_PFC_R8A77961 if ARCH_R8A77961 @@ -103,10 +102,6 @@ config PINCTRL_PFC_R8A7790 bool "pin control support for R-Car H2" if COMPILE_TEST select PINCTRL_SH_PFC -config PINCTRL_PFC_R8A77950 - bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST - select PINCTRL_SH_PFC - config PINCTRL_PFC_R8A77951 bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST select PINCTRL_SH_PFC diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 558b30ce0dec..3e776955bd4b 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o -obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index c91102d3f1d1..0c8d081da6a8 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -573,23 +573,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7794_pinmux_info, }, #endif -/* - * Both r8a7795 entries must be present to make sanity checks work, but only - * the first entry is actually used. - * R-Car H3 ES1.x is matched using soc_device_match() instead. - */ #ifdef CONFIG_PINCTRL_PFC_R8A77951 { .compatible = "renesas,pfc-r8a7795", .data = &r8a77951_pinmux_info, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77950 - { - .compatible = "renesas,pfc-r8a7795", - .data = &r8a77950_pinmux_info, - }, -#endif #ifdef CONFIG_PINCTRL_PFC_R8A77960 { .compatible = "renesas,pfc-r8a7796", @@ -656,7 +645,7 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &sh73a0_pinmux_info, }, #endif - { }, + { /* sentinel */ } }; #endif @@ -1125,9 +1114,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) } } - if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) { + if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) { if (!info->ops || !info->ops->pin_to_pocctrl) - sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n"); + sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n"); else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n", pin->name); @@ -1309,41 +1298,15 @@ free_regs: static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} #endif /* !DEBUG */ -#ifdef CONFIG_OF -static const void *sh_pfc_quirk_match(void) -{ -#ifdef CONFIG_PINCTRL_PFC_R8A77950 - const struct soc_device_attribute *match; - static const struct soc_device_attribute quirks[] = { - { - .soc_id = "r8a7795", .revision = "ES1.*", - .data = &r8a77950_pinmux_info, - }, - { /* sentinel */ } - }; - - match = soc_device_match(quirks); - if (match) - return match->data; -#endif /* CONFIG_PINCTRL_PFC_R8A77950 */ - - return NULL; -} -#endif /* CONFIG_OF */ - static int sh_pfc_probe(struct platform_device *pdev) { const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; -#ifdef CONFIG_OF - if (pdev->dev.of_node) { - info = sh_pfc_quirk_match(); - if (!info) - info = of_device_get_match_data(&pdev->dev); - } else -#endif + if (pdev->dev.of_node) + info = of_device_get_match_data(&pdev->dev); + else info = (const void *)platform_get_device_id(pdev)->driver_data; pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); @@ -1446,7 +1409,7 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_SHX3 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, #endif - { }, + { /* sentinel */ } }; static struct platform_driver sh_pfc_driver = { diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c index 1d8b540110f2..86d18b03668e 100644 --- a/drivers/pinctrl/renesas/pfc-emev2.c +++ b/drivers/pinctrl/renesas/pfc-emev2.c @@ -1644,7 +1644,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0, )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info emev2_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c index dbfc46fe2f27..be0a4914eab3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a73a4.c +++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c @@ -2384,7 +2384,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL8CR_00_0, MSEL8CR_00_1, )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2510,7 +2510,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA, )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_irq pinmux_irqs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c index 6dcd39918daf..9ee3b700a3d3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7740.c +++ b/drivers/pinctrl/renesas/pfc-r8a7740.c @@ -3348,7 +3348,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL5CR_0_0, MSEL5CR_0_1, )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -3452,7 +3452,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_irq pinmux_irqs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c index b5725c3ed2b6..ed48b043763f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77470.c +++ b/drivers/pinctrl/renesas/pfc-r8a77470.c @@ -13,24 +13,24 @@ #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -38,12 +38,12 @@ PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -3252,7 +3252,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SSI0 [2] */ FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, )) }, - { }, + { /* sentinel */ } }; static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index 35bdb9af8160..c52761d80f7b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -2832,7 +2832,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C1_A, FN_SEL_I2C1_B, )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_bias_reg pinmux_bias_regs[] = { @@ -3040,7 +3040,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c index fcc8ea48881f..1172a359384d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7779.c +++ b/drivers/pinctrl/renesas/pfc-r8a7779.c @@ -12,13 +12,76 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx), \ - PORT_GP_9(6, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(2, 1, fn, sfx), \ + PORT_GP_1(2, 2, fn, sfx), \ + PORT_GP_1(2, 3, fn, sfx), \ + PORT_GP_1(2, 4, fn, sfx), \ + PORT_GP_1(2, 5, fn, sfx), \ + PORT_GP_1(2, 6, fn, sfx), \ + PORT_GP_1(2, 7, fn, sfx), \ + PORT_GP_1(2, 8, fn, sfx), \ + PORT_GP_1(2, 9, fn, sfx), \ + PORT_GP_1(2, 10, fn, sfx), \ + PORT_GP_1(2, 11, fn, sfx), \ + PORT_GP_1(2, 12, fn, sfx), \ + PORT_GP_1(2, 13, fn, sfx), \ + PORT_GP_1(2, 14, fn, sfx), \ + PORT_GP_1(2, 15, fn, sfx), \ + PORT_GP_1(2, 16, fn, sfx), \ + PORT_GP_1(2, 17, fn, sfx), \ + PORT_GP_1(2, 18, fn, sfx), \ + PORT_GP_1(2, 19, fn, sfx), \ + PORT_GP_1(2, 20, fn, sfx), \ + PORT_GP_1(2, 21, fn, sfx), \ + PORT_GP_1(2, 22, fn, sfx), \ + PORT_GP_1(2, 23, fn, sfx), \ + PORT_GP_1(2, 24, fn, sfx), \ + PORT_GP_1(2, 25, fn, sfx), \ + PORT_GP_1(2, 26, fn, sfx), \ + PORT_GP_1(2, 27, fn, sfx), \ + PORT_GP_1(2, 28, fn, sfx), \ + PORT_GP_1(2, 29, fn, sfx), \ + PORT_GP_CFG_1(2, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(2, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_25(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(3, 25, fn, sfx), \ + PORT_GP_1(3, 26, fn, sfx), \ + PORT_GP_1(3, 27, fn, sfx), \ + PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_9(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D0, "D0", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D1, "D1", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D2, "D2", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D3, "D3", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D4, "D4", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D5, "D5", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D6, "D6", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D7, "D7", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D8, "D8", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D9, "D9", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D10, "D10", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D11, "D11", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D12, "D12", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D13, "D13", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D14, "D14", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(D15, "D15", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -1390,8 +1453,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - DU0 -------------------------------------------------------------------- */ @@ -1962,6 +2034,67 @@ static const unsigned int mmc1_ctrl_pins[] = { static const unsigned int mmc1_ctrl_mux[] = { MMC1_CMD_MARK, MMC1_CLK_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(1, 3), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(0, 12), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm0_c_pins[] = { + RCAR_GP_PIN(4, 5), +}; +static const unsigned int pwm0_c_mux[] = { + PWM0_C_MARK, +}; +static const unsigned int pwm0_d_pins[] = { + RCAR_GP_PIN(4, 18), +}; +static const unsigned int pwm0_d_mux[] = { + PWM0_D_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(4, 28), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(3, 25), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(3, 26), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(3, 27), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(4, 17), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(1, 2), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RXD, TXD */ @@ -2699,6 +2832,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { BUS_DATA_PIN_GROUP(mmc1_data, 4), BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm0_c), + SH_PFC_PIN_GROUP(pwm0_d), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2912,6 +3055,37 @@ static const char * const mmc1_groups[] = { "mmc1_ctrl", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", + "pwm0_c", + "pwm0_d", +}; + +static const char * const pwm1_groups[] = { + "pwm1", +}; + +static const char * const pwm2_groups[] = { + "pwm2", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const pwm5_groups[] = { + "pwm5", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -3075,6 +3249,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3919,11 +4100,259 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C1 [2] */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 )) }, - { }, + { /* sentinel */ } +}; + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 2), /* A0 */ + [ 1] = RCAR_GP_PIN(5, 0), /* A1 */ + [ 2] = RCAR_GP_PIN(5, 1), /* A2 */ + [ 3] = RCAR_GP_PIN(5, 2), /* A3 */ + [ 4] = RCAR_GP_PIN(5, 3), /* A4 */ + [ 5] = RCAR_GP_PIN(5, 4), /* A5 */ + [ 6] = RCAR_GP_PIN(5, 5), /* A6 */ + [ 7] = RCAR_GP_PIN(5, 6), /* A7 */ + [ 8] = RCAR_GP_PIN(5, 7), /* A8 */ + [ 9] = RCAR_GP_PIN(5, 8), /* A9 */ + [10] = RCAR_GP_PIN(5, 9), /* A10 */ + [11] = RCAR_GP_PIN(5, 10), /* A11 */ + [12] = RCAR_GP_PIN(5, 11), /* A12 */ + [13] = RCAR_GP_PIN(5, 12), /* A13 */ + [14] = RCAR_GP_PIN(5, 13), /* A14 */ + [15] = RCAR_GP_PIN(5, 14), /* A15 */ + [16] = RCAR_GP_PIN(5, 15), /* A16 */ + [17] = RCAR_GP_PIN(0, 3), /* A17 */ + [18] = RCAR_GP_PIN(0, 4), /* A18 */ + [19] = RCAR_GP_PIN(0, 5), /* A19 */ + [20] = RCAR_GP_PIN(0, 6), /* A20 */ + [21] = RCAR_GP_PIN(0, 7), /* A21 */ + [22] = RCAR_GP_PIN(0, 8), /* A22 */ + [23] = RCAR_GP_PIN(0, 9), /* A23 */ + [24] = RCAR_GP_PIN(0, 10), /* A24 */ + [25] = RCAR_GP_PIN(0, 11), /* A25 */ + [26] = RCAR_GP_PIN(0, 15), /* EX_CS0# */ + [27] = RCAR_GP_PIN(0, 16), /* EX_CS1# */ + [28] = RCAR_GP_PIN(0, 17), /* EX_CS2# */ + [29] = RCAR_GP_PIN(0, 18), /* EX_CS3# */ + [30] = RCAR_GP_PIN(0, 19), /* EX_CS4# */ + [31] = RCAR_GP_PIN(0, 20), /* EX_CS5# */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) { + [ 0] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [ 1] = RCAR_GP_PIN(0, 21), /* BS# */ + [ 2] = RCAR_GP_PIN(0, 22), /* RD/WR# */ + [ 3] = RCAR_GP_PIN(5, 17), /* WE0# */ + [ 4] = RCAR_GP_PIN(5, 18), /* WE1# */ + [ 5] = RCAR_GP_PIN(5, 19), /* EX_WAIT0 */ + [ 6] = RCAR_GP_PIN(0, 0), /* AVS1 */ + [ 7] = RCAR_GP_PIN(0, 1), /* AVS2 */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = PIN_TRST_N, /* TRST# */ + [11] = PIN_TCK, /* TCK */ + [12] = PIN_TMS, /* TMS */ + [13] = PIN_TDI, /* TDI */ + [14] = PIN_TDO, /* TDO */ + [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [16] = PIN_D0, /* D0 */ + [17] = PIN_D1, /* D1 */ + [18] = PIN_D2, /* D2 */ + [19] = PIN_D3, /* D3 */ + [20] = PIN_D4, /* D4 */ + [21] = PIN_D5, /* D5 */ + [22] = PIN_D6, /* D6 */ + [23] = PIN_D7, /* D7 */ + [24] = PIN_D8, /* D8 */ + [25] = PIN_D9, /* D9 */ + [26] = PIN_D10, /* D10 */ + [27] = PIN_D11, /* D11 */ + [28] = PIN_D12, /* D12 */ + [29] = PIN_D13, /* D13 */ + [30] = PIN_D14, /* D14 */ + [31] = PIN_D15, /* D15 */ + } }, + { PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 23), /* DU0_DR0 */ + [ 1] = RCAR_GP_PIN(0, 24), /* DU0_DR1 */ + [ 2] = RCAR_GP_PIN(5, 23), /* DU0_DR2 */ + [ 3] = RCAR_GP_PIN(5, 24), /* DU0_DR3 */ + [ 4] = RCAR_GP_PIN(5, 25), /* DU0_DR4 */ + [ 5] = RCAR_GP_PIN(5, 26), /* DU0_DR5 */ + [ 6] = RCAR_GP_PIN(5, 27), /* DU0_DR6 */ + [ 7] = RCAR_GP_PIN(5, 28), /* DU0_DR7 */ + [ 8] = RCAR_GP_PIN(0, 25), /* DU0_DG0 */ + [ 9] = RCAR_GP_PIN(0, 26), /* DU0_DG1 */ + [10] = RCAR_GP_PIN(5, 29), /* DU0_DG2 */ + [11] = RCAR_GP_PIN(5, 30), /* DU0_DG3 */ + [12] = RCAR_GP_PIN(5, 31), /* DU0_DG4 */ + [13] = RCAR_GP_PIN(6, 0), /* DU0_DG5 */ + [14] = RCAR_GP_PIN(6, 1), /* DU0_DG6 */ + [15] = RCAR_GP_PIN(6, 2), /* DU0_DG7 */ + [16] = RCAR_GP_PIN(0, 27), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(0, 28), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(6, 3), /* DU0_DB2 */ + [19] = RCAR_GP_PIN(6, 4), /* DU0_DB3 */ + [20] = RCAR_GP_PIN(6, 5), /* DU0_DB4 */ + [21] = RCAR_GP_PIN(6, 6), /* DU0_DB5 */ + [22] = RCAR_GP_PIN(6, 7), /* DU0_DB6 */ + [23] = RCAR_GP_PIN(6, 8), /* DU0_DB7 */ + [24] = RCAR_GP_PIN(0, 29), /* DU0_DOTCLKIN */ + [25] = RCAR_GP_PIN(5, 20), /* DU0_DOTCLKOUT0 */ + [26] = RCAR_GP_PIN(5, 21), /* DU0_HSYNC */ + [27] = RCAR_GP_PIN(5, 22), /* DU0_VSYNC */ + [28] = RCAR_GP_PIN(0, 31), /* DU0_EXODDF */ + [29] = RCAR_GP_PIN(1, 0), /* DU0_DISP */ + [30] = RCAR_GP_PIN(1, 1), /* DU0_CDE */ + [31] = RCAR_GP_PIN(0, 30), /* DU0_DOTCLKOUT1 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 2), /* DU1_DR0 */ + [ 1] = RCAR_GP_PIN(1, 3), /* DU1_DR1 */ + [ 2] = RCAR_GP_PIN(1, 4), /* DU1_DR2 */ + [ 3] = RCAR_GP_PIN(1, 5), /* DU1_DR3 */ + [ 4] = RCAR_GP_PIN(1, 6), /* DU1_DR4 */ + [ 5] = RCAR_GP_PIN(1, 7), /* DU1_DR5 */ + [ 6] = RCAR_GP_PIN(1, 8), /* DU1_DR6 */ + [ 7] = RCAR_GP_PIN(1, 9), /* DU1_DR7 */ + [ 8] = RCAR_GP_PIN(1, 10), /* DU1_DG0 */ + [ 9] = RCAR_GP_PIN(1, 11), /* DU1_DG1 */ + [10] = RCAR_GP_PIN(1, 12), /* DU1_DG2 */ + [11] = RCAR_GP_PIN(1, 13), /* DU1_DG3 */ + [12] = RCAR_GP_PIN(1, 14), /* DU1_DG4 */ + [13] = RCAR_GP_PIN(1, 15), /* DU1_DG5 */ + [14] = RCAR_GP_PIN(1, 16), /* DU1_DG6 */ + [15] = RCAR_GP_PIN(1, 17), /* DU1_DG7 */ + [16] = RCAR_GP_PIN(1, 18), /* DU1_DB0 */ + [17] = RCAR_GP_PIN(1, 19), /* DU1_DB1 */ + [18] = RCAR_GP_PIN(1, 20), /* DU1_DB2 */ + [19] = RCAR_GP_PIN(1, 21), /* DU1_DB3 */ + [20] = RCAR_GP_PIN(1, 22), /* DU1_DB4 */ + [21] = RCAR_GP_PIN(1, 23), /* DU1_DB5 */ + [22] = RCAR_GP_PIN(1, 24), /* DU1_DB6 */ + [23] = RCAR_GP_PIN(1, 25), /* DU1_DB7 */ + [24] = RCAR_GP_PIN(1, 26), /* DU1_DOTCLKIN */ + [25] = RCAR_GP_PIN(1, 27), /* DU1_DOTCLKOUT */ + [26] = RCAR_GP_PIN(1, 28), /* DU1_HSYNC */ + [27] = RCAR_GP_PIN(1, 29), /* DU1_VSYNC */ + [28] = RCAR_GP_PIN(1, 30), /* DU1_EXODDF */ + [29] = RCAR_GP_PIN(1, 31), /* DU1_DISP */ + [30] = RCAR_GP_PIN(2, 0), /* DU1_CDE */ + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 30), /* VI1_CLK */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = RCAR_GP_PIN(2, 31), /* VI1_HSYNC# */ + [ 4] = RCAR_GP_PIN(3, 0), /* VI1_VSYNC# */ + [ 5] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */ + [ 6] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */ + [ 7] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */ + [ 8] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */ + [ 9] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */ + [10] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */ + [11] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */ + [12] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */ + [13] = RCAR_GP_PIN(3, 9), /* VI1_G0 */ + [14] = RCAR_GP_PIN(3, 10), /* VI1_G1 */ + [15] = RCAR_GP_PIN(3, 11), /* VI1_G2 */ + [16] = RCAR_GP_PIN(3, 12), /* VI1_G3 */ + [17] = RCAR_GP_PIN(3, 13), /* VI1_G4 */ + [18] = RCAR_GP_PIN(3, 14), /* VI1_G5 */ + [19] = RCAR_GP_PIN(3, 15), /* VI1_G6 */ + [20] = RCAR_GP_PIN(3, 16), /* VI1_G7 */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 30), /* SSI_SCK0129 */ + [ 1] = RCAR_GP_PIN(3, 31), /* SSI_WS0129 */ + [ 2] = RCAR_GP_PIN(4, 0), /* SSI_SDATA0 */ + [ 3] = RCAR_GP_PIN(4, 1), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(4, 2), /* SSI_SDATA2 */ + [ 5] = RCAR_GP_PIN(4, 3), /* SSI_SCK34 */ + [ 6] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */ + [ 7] = RCAR_GP_PIN(4, 5), /* SSI_SDATA3 */ + [ 8] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4 */ + [ 9] = RCAR_GP_PIN(4, 7), /* SSI_SCK5 */ + [10] = RCAR_GP_PIN(4, 8), /* SSI_WS5 */ + [11] = RCAR_GP_PIN(4, 9), /* SSI_SDATA5 */ + [12] = RCAR_GP_PIN(4, 10), /* SSI_SCK6 */ + [13] = RCAR_GP_PIN(4, 11), /* SSI_WS6 */ + [14] = RCAR_GP_PIN(4, 12), /* SSI_SDATA6 */ + [15] = RCAR_GP_PIN(4, 13), /* SSI_SCK78 */ + [16] = RCAR_GP_PIN(4, 14), /* SSI_WS78 */ + [17] = RCAR_GP_PIN(4, 15), /* SSI_SDATA7 */ + [18] = RCAR_GP_PIN(4, 16), /* SSI_SDATA8 */ + [19] = SH_PFC_PIN_NONE, + [20] = RCAR_GP_PIN(3, 17), /* SD0_CLK */ + [21] = RCAR_GP_PIN(3, 18), /* SD0_CMD */ + [22] = RCAR_GP_PIN(3, 21), /* SD0_DAT0 */ + [23] = RCAR_GP_PIN(3, 22), /* SD0_DAT1 */ + [24] = RCAR_GP_PIN(3, 23), /* SD0_DAT2 */ + [25] = RCAR_GP_PIN(3, 24), /* SD0_DAT3 */ + [26] = RCAR_GP_PIN(3, 19), /* SD0_CD */ + [27] = RCAR_GP_PIN(3, 20), /* SD0_WP */ + [28] = RCAR_GP_PIN(3, 28), /* AUDIO_CLKA */ + [29] = RCAR_GP_PIN(3, 29), /* AUDIO_CLKB */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR6", 0xfffc0118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 26), /* PENC0 */ + [ 1] = RCAR_GP_PIN(4, 27), /* PENC1 */ + [ 2] = RCAR_GP_PIN(4, 28), /* PENC2 */ + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = RCAR_GP_PIN(4, 20), /* HTX0 */ + [ 6] = RCAR_GP_PIN(4, 21), /* HRX0 */ + [ 7] = RCAR_GP_PIN(4, 17), /* HSCK0 */ + [ 8] = RCAR_GP_PIN(4, 18), /* HCTS0# */ + [ 9] = RCAR_GP_PIN(4, 19), /* HRTS0# */ + [10] = RCAR_GP_PIN(4, 22), /* HSPI_CLK0 */ + [11] = RCAR_GP_PIN(4, 23), /* HSPI_CS0# */ + [12] = RCAR_GP_PIN(4, 24), /* HSPI_TX0 */ + [13] = RCAR_GP_PIN(4, 25), /* HSPI_RX0 */ + [14] = RCAR_GP_PIN(4, 29), /* FMCLK */ + [15] = RCAR_GP_PIN(4, 30), /* BPFCLK */ + [16] = RCAR_GP_PIN(4, 31), /* FMIN */ + [17] = RCAR_GP_PIN(0, 12), /* CLKOUT */ + [18] = RCAR_GP_PIN(0, 13), /* CS0# */ + [19] = RCAR_GP_PIN(0, 14), /* CS1#/A26 */ + [20] = RCAR_GP_PIN(5, 16), /* RD# */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + +static const struct sh_pfc_soc_operations r8a7779_pfc_ops = { + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7779_pinmux_info = { .name = "r8a7779_pfc", + .ops = &r8a7779_pfc_ops, .unlock_reg = 0xfffc0000, /* PMMR */ @@ -3937,6 +4366,7 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index ee21d650991b..791e089d47db 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -24,7 +24,7 @@ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) @@ -5824,7 +5824,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C1 [2] */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) }, - { }, + { /* sentinel */ } }; static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index d57458504117..d9e5ce0dfb5b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -22,7 +22,7 @@ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -6552,7 +6552,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, /* RESERVED [6] */ )) }, - { }, + { /* sentinel */ } }; static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -6874,7 +6874,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a7791_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 808a85d62415..2c51c32b8e09 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -2625,7 +2625,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_1_0 [2] */ FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_bias_reg pinmux_bias_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 668643553a70..e800fef91ddb 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -42,30 +42,30 @@ PORT_GP_1(5, 25, fn, sfx), \ PORT_GP_1(5, 26, fn, sfx), \ PORT_GP_1(5, 27, fn, sfx), \ - PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) @@ -5512,7 +5512,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SSI9_0, FN_SEL_SSI9_1, /* RESERVED [12] */ )) }, - { }, + { /* sentinel */ } }; static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c deleted file mode 100644 index cc66c6de045c..000000000000 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ /dev/null @@ -1,5947 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * R8A77950 processor support - PFC hardware block. - * - * Copyright (C) 2015-2017 Renesas Electronics Corporation - */ - -#include <linux/errno.h> -#include <linux/kernel.h> - -#include "sh_pfc.h" - -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) - -#define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) - -#define CPU_ALL_NOGP(fn) \ - PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ - PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ - PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) - -/* - * F_() : just information - * FM() : macro for FN_xxx / xxx_MARK - */ - -/* GPSR0 */ -#define GPSR0_15 F_(D15, IP7_11_8) -#define GPSR0_14 F_(D14, IP7_7_4) -#define GPSR0_13 F_(D13, IP7_3_0) -#define GPSR0_12 F_(D12, IP6_31_28) -#define GPSR0_11 F_(D11, IP6_27_24) -#define GPSR0_10 F_(D10, IP6_23_20) -#define GPSR0_9 F_(D9, IP6_19_16) -#define GPSR0_8 F_(D8, IP6_15_12) -#define GPSR0_7 F_(D7, IP6_11_8) -#define GPSR0_6 F_(D6, IP6_7_4) -#define GPSR0_5 F_(D5, IP6_3_0) -#define GPSR0_4 F_(D4, IP5_31_28) -#define GPSR0_3 F_(D3, IP5_27_24) -#define GPSR0_2 F_(D2, IP5_23_20) -#define GPSR0_1 F_(D1, IP5_19_16) -#define GPSR0_0 F_(D0, IP5_15_12) - -/* GPSR1 */ -#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) -#define GPSR1_26 F_(WE1_N, IP5_7_4) -#define GPSR1_25 F_(WE0_N, IP5_3_0) -#define GPSR1_24 F_(RD_WR_N, IP4_31_28) -#define GPSR1_23 F_(RD_N, IP4_27_24) -#define GPSR1_22 F_(BS_N, IP4_23_20) -#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) -#define GPSR1_20 F_(CS0_N, IP4_15_12) -#define GPSR1_19 F_(A19, IP4_11_8) -#define GPSR1_18 F_(A18, IP4_7_4) -#define GPSR1_17 F_(A17, IP4_3_0) -#define GPSR1_16 F_(A16, IP3_31_28) -#define GPSR1_15 F_(A15, IP3_27_24) -#define GPSR1_14 F_(A14, IP3_23_20) -#define GPSR1_13 F_(A13, IP3_19_16) -#define GPSR1_12 F_(A12, IP3_15_12) -#define GPSR1_11 F_(A11, IP3_11_8) -#define GPSR1_10 F_(A10, IP3_7_4) -#define GPSR1_9 F_(A9, IP3_3_0) -#define GPSR1_8 F_(A8, IP2_31_28) -#define GPSR1_7 F_(A7, IP2_27_24) -#define GPSR1_6 F_(A6, IP2_23_20) -#define GPSR1_5 F_(A5, IP2_19_16) -#define GPSR1_4 F_(A4, IP2_15_12) -#define GPSR1_3 F_(A3, IP2_11_8) -#define GPSR1_2 F_(A2, IP2_7_4) -#define GPSR1_1 F_(A1, IP2_3_0) -#define GPSR1_0 F_(A0, IP1_31_28) - -/* GPSR2 */ -#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) -#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) -#define GPSR2_12 F_(AVB_LINK, IP0_15_12) -#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) -#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) -#define GPSR2_9 F_(AVB_MDC, IP0_3_0) -#define GPSR2_8 F_(PWM2_A, IP1_27_24) -#define GPSR2_7 F_(PWM1_A, IP1_23_20) -#define GPSR2_6 F_(PWM0, IP1_19_16) -#define GPSR2_5 F_(IRQ5, IP1_15_12) -#define GPSR2_4 F_(IRQ4, IP1_11_8) -#define GPSR2_3 F_(IRQ3, IP1_7_4) -#define GPSR2_2 F_(IRQ2, IP1_3_0) -#define GPSR2_1 F_(IRQ1, IP0_31_28) -#define GPSR2_0 F_(IRQ0, IP0_27_24) - -/* GPSR3 */ -#define GPSR3_15 F_(SD1_WP, IP10_23_20) -#define GPSR3_14 F_(SD1_CD, IP10_19_16) -#define GPSR3_13 F_(SD0_WP, IP10_15_12) -#define GPSR3_12 F_(SD0_CD, IP10_11_8) -#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) -#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) -#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) -#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) -#define GPSR3_7 F_(SD1_CMD, IP8_15_12) -#define GPSR3_6 F_(SD1_CLK, IP8_11_8) -#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) -#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) -#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) -#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) -#define GPSR3_1 F_(SD0_CMD, IP7_23_20) -#define GPSR3_0 F_(SD0_CLK, IP7_19_16) - -/* GPSR4 */ -#define GPSR4_17 FM(SD3_DS) -#define GPSR4_16 F_(SD3_DAT7, IP10_7_4) -#define GPSR4_15 F_(SD3_DAT6, IP10_3_0) -#define GPSR4_14 F_(SD3_DAT5, IP9_31_28) -#define GPSR4_13 F_(SD3_DAT4, IP9_27_24) -#define GPSR4_12 FM(SD3_DAT3) -#define GPSR4_11 FM(SD3_DAT2) -#define GPSR4_10 FM(SD3_DAT1) -#define GPSR4_9 FM(SD3_DAT0) -#define GPSR4_8 FM(SD3_CMD) -#define GPSR4_7 FM(SD3_CLK) -#define GPSR4_6 F_(SD2_DS, IP9_23_20) -#define GPSR4_5 F_(SD2_DAT3, IP9_19_16) -#define GPSR4_4 F_(SD2_DAT2, IP9_15_12) -#define GPSR4_3 F_(SD2_DAT1, IP9_11_8) -#define GPSR4_2 F_(SD2_DAT0, IP9_7_4) -#define GPSR4_1 FM(SD2_CMD) -#define GPSR4_0 F_(SD2_CLK, IP9_3_0) - -/* GPSR5 */ -#define GPSR5_25 F_(MLB_DAT, IP13_19_16) -#define GPSR5_24 F_(MLB_SIG, IP13_15_12) -#define GPSR5_23 F_(MLB_CLK, IP13_11_8) -#define GPSR5_22 FM(MSIOF0_RXD) -#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4) -#define GPSR5_20 FM(MSIOF0_TXD) -#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0) -#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28) -#define GPSR5_17 FM(MSIOF0_SCK) -#define GPSR5_16 F_(HRTS0_N, IP12_27_24) -#define GPSR5_15 F_(HCTS0_N, IP12_23_20) -#define GPSR5_14 F_(HTX0, IP12_19_16) -#define GPSR5_13 F_(HRX0, IP12_15_12) -#define GPSR5_12 F_(HSCK0, IP12_11_8) -#define GPSR5_11 F_(RX2_A, IP12_7_4) -#define GPSR5_10 F_(TX2_A, IP12_3_0) -#define GPSR5_9 F_(SCK2, IP11_31_28) -#define GPSR5_8 F_(RTS1_N, IP11_27_24) -#define GPSR5_7 F_(CTS1_N, IP11_23_20) -#define GPSR5_6 F_(TX1_A, IP11_19_16) -#define GPSR5_5 F_(RX1_A, IP11_15_12) -#define GPSR5_4 F_(RTS0_N, IP11_11_8) -#define GPSR5_3 F_(CTS0_N, IP11_7_4) -#define GPSR5_2 F_(TX0, IP11_3_0) -#define GPSR5_1 F_(RX0, IP10_31_28) -#define GPSR5_0 F_(SCK0, IP10_27_24) - -/* GPSR6 */ -#define GPSR6_31 F_(USB31_OVC, IP17_7_4) -#define GPSR6_30 F_(USB31_PWEN, IP17_3_0) -#define GPSR6_29 F_(USB30_OVC, IP16_31_28) -#define GPSR6_28 F_(USB30_PWEN, IP16_27_24) -#define GPSR6_27 F_(USB1_OVC, IP16_23_20) -#define GPSR6_26 F_(USB1_PWEN, IP16_19_16) -#define GPSR6_25 F_(USB0_OVC, IP16_15_12) -#define GPSR6_24 F_(USB0_PWEN, IP16_11_8) -#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4) -#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0) -#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28) -#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24) -#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20) -#define GPSR6_18 F_(SSI_WS78, IP15_19_16) -#define GPSR6_17 F_(SSI_SCK78, IP15_15_12) -#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8) -#define GPSR6_15 F_(SSI_WS6, IP15_7_4) -#define GPSR6_14 F_(SSI_SCK6, IP15_3_0) -#define GPSR6_13 FM(SSI_SDATA5) -#define GPSR6_12 FM(SSI_WS5) -#define GPSR6_11 FM(SSI_SCK5) -#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28) -#define GPSR6_9 F_(SSI_WS4, IP14_27_24) -#define GPSR6_8 F_(SSI_SCK4, IP14_23_20) -#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16) -#define GPSR6_6 F_(SSI_WS349, IP14_15_12) -#define GPSR6_5 F_(SSI_SCK349, IP14_11_8) -#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) -#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) -#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) -#define GPSR6_1 F_(SSI_WS01239, IP13_27_24) -#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20) - -/* GPSR7 */ -#define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(GP7_02) -#define GPSR7_1 FM(AVS2) -#define GPSR7_0 FM(AVS1) - - -/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ -#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ -#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ -#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ -#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -#define PINMUX_GPSR \ -\ - GPSR6_31 \ - GPSR6_30 \ - GPSR6_29 \ - GPSR6_28 \ - GPSR1_27 GPSR6_27 \ - GPSR1_26 GPSR6_26 \ - GPSR1_25 GPSR5_25 GPSR6_25 \ - GPSR1_24 GPSR5_24 GPSR6_24 \ - GPSR1_23 GPSR5_23 GPSR6_23 \ - GPSR1_22 GPSR5_22 GPSR6_22 \ - GPSR1_21 GPSR5_21 GPSR6_21 \ - GPSR1_20 GPSR5_20 GPSR6_20 \ - GPSR1_19 GPSR5_19 GPSR6_19 \ - GPSR1_18 GPSR5_18 GPSR6_18 \ - GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ - GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ -GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ -GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ -GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ -GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ -GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ -GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ -GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ -GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ -GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ -GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ -GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ -GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ -GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ -GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ -GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ -GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 - -#define PINMUX_IPSR \ -\ -FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ -FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ -FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ -FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ -FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ -FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ -FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ -FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ -\ -FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ -FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ -FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ -FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ -FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ -FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ -FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ -FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ -\ -FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ -FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ -FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ -FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ -FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ -FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ -FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ -FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ -\ -FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ -FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ -FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ -FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ -FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ -FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ -FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ -FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ -\ -FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \ -FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \ -FM(IP16_11_8) IP16_11_8 \ -FM(IP16_15_12) IP16_15_12 \ -FM(IP16_19_16) IP16_19_16 \ -FM(IP16_23_20) IP16_23_20 \ -FM(IP16_27_24) IP16_27_24 \ -FM(IP16_31_28) IP16_31_28 - -/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) -#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) -#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) -#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) -#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) -#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) -#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1) -#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1) -#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) -#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) -#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) -#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) -#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1) -#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1) -#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) -#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) -#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) -#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) -#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) -#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3) - -/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) -#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) -#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) -#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) -#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) -#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) -#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) -#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) -#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) -#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) -#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) -#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) -#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) -#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) -#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) -#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) -#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) -#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) -#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) -#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) - -/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ -#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) -#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) -#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) -#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) - -#define PINMUX_MOD_SELS\ -\ - MOD_SEL1_31_30 MOD_SEL2_31 \ -MOD_SEL0_30_29 MOD_SEL2_30 \ - MOD_SEL1_29_28_27 MOD_SEL2_29 \ -MOD_SEL0_28_27 \ -\ -MOD_SEL0_26_25_24 MOD_SEL1_26 \ - MOD_SEL1_25_24 \ -\ -MOD_SEL0_23 MOD_SEL1_23_22_21 \ -MOD_SEL0_22 \ -MOD_SEL0_21_20 \ - MOD_SEL1_20 \ -MOD_SEL0_19 MOD_SEL1_19 \ -MOD_SEL0_18 MOD_SEL1_18_17 \ -MOD_SEL0_17 \ -MOD_SEL0_16_15 MOD_SEL1_16 \ - MOD_SEL1_15_14 \ -MOD_SEL0_14 \ -MOD_SEL0_13 MOD_SEL1_13 \ -MOD_SEL0_12 MOD_SEL1_12 \ -MOD_SEL0_11 MOD_SEL1_11 \ -MOD_SEL0_10 MOD_SEL1_10 \ -MOD_SEL0_9 MOD_SEL1_9 \ -MOD_SEL0_8 \ -MOD_SEL0_7_6 \ - MOD_SEL1_6 \ -MOD_SEL0_5_4 MOD_SEL1_5 \ - MOD_SEL1_4 \ -MOD_SEL0_3 MOD_SEL1_3 \ -MOD_SEL0_2_1 MOD_SEL1_2 \ - MOD_SEL1_1 \ - MOD_SEL1_0 MOD_SEL2_0 - -/* - * These pins are not able to be muxed but have other properties - * that can be set, such as drive-strength or pull-up/pull-down enable. - */ -#define PINMUX_STATIC \ - FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ - FM(QSPI0_IO2) FM(QSPI0_IO3) \ - FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ - FM(QSPI1_IO2) FM(QSPI1_IO3) \ - FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ - FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ - FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ - FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ - FM(CLKOUT) FM(PRESETOUT) \ - FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ - FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) - -#define PINMUX_PHYS \ - FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - -#define F_(x, y) -#define FM(x) FN_##x, - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - PINMUX_GPSR - PINMUX_IPSR - PINMUX_MOD_SELS - PINMUX_FUNCTION_END, -#undef F_ -#undef FM - -#define F_(x, y) -#define FM(x) x##_MARK, - PINMUX_MARK_BEGIN, - PINMUX_GPSR - PINMUX_IPSR - PINMUX_MOD_SELS - PINMUX_STATIC - PINMUX_PHYS - PINMUX_MARK_END, -#undef F_ -#undef FM -}; - -static const u16 pinmux_data[] = { - PINMUX_DATA_GP_ALL(), - - PINMUX_SINGLE(AVS1), - PINMUX_SINGLE(AVS2), - PINMUX_SINGLE(GP7_02), - PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(MSIOF0_RXD), - PINMUX_SINGLE(MSIOF0_SCK), - PINMUX_SINGLE(MSIOF0_TXD), - PINMUX_SINGLE(SD2_CMD), - PINMUX_SINGLE(SD3_CLK), - PINMUX_SINGLE(SD3_CMD), - PINMUX_SINGLE(SD3_DAT0), - PINMUX_SINGLE(SD3_DAT1), - PINMUX_SINGLE(SD3_DAT2), - PINMUX_SINGLE(SD3_DAT3), - PINMUX_SINGLE(SD3_DS), - PINMUX_SINGLE(SSI_SCK5), - PINMUX_SINGLE(SSI_SDATA5), - PINMUX_SINGLE(SSI_WS5), - - /* IPSR0 */ - PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), - PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), - - PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), - PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), - - PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), - PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), - - PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), - PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), - PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), - PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), - - PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), - PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), - PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), - PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), - PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), - - PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), - PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), - PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), - PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), - PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), - - /* IPSR1 */ - PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), - PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), - PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), - PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), - - PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), - PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), - PINMUX_IPSR_GPSR(IP1_7_4, A25), - PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), - PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), - - PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), - PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), - PINMUX_IPSR_GPSR(IP1_11_8, A24), - PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), - PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), - - PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), - PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), - PINMUX_IPSR_GPSR(IP1_15_12, A23), - PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), - PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), - - PINMUX_IPSR_GPSR(IP1_19_16, PWM0), - PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), - PINMUX_IPSR_GPSR(IP1_19_16, A22), - PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), - - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), - - PINMUX_IPSR_GPSR(IP1_31_28, A0), - PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), - PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), - PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), - PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), - PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), - - /* IPSR2 */ - PINMUX_IPSR_GPSR(IP2_3_0, A1), - PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), - PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), - PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), - PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), - PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), - - PINMUX_IPSR_GPSR(IP2_7_4, A2), - PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), - PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), - PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), - PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), - PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), - - PINMUX_IPSR_GPSR(IP2_11_8, A3), - PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), - PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), - PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), - PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), - PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), - - PINMUX_IPSR_GPSR(IP2_15_12, A4), - PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), - PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), - PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), - PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), - PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), - - PINMUX_IPSR_GPSR(IP2_19_16, A5), - PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), - PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), - PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), - PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), - PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), - PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), - - PINMUX_IPSR_GPSR(IP2_23_20, A6), - PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), - PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), - PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), - PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), - PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), - - PINMUX_IPSR_GPSR(IP2_27_24, A7), - PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), - PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), - PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), - PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), - PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), - - PINMUX_IPSR_GPSR(IP2_31_28, A8), - PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), - PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), - PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), - PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), - - /* IPSR3 */ - PINMUX_IPSR_GPSR(IP3_3_0, A9), - PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), - PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), - - PINMUX_IPSR_GPSR(IP3_7_4, A10), - PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), - PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), - - PINMUX_IPSR_GPSR(IP3_11_8, A11), - PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), - PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), - PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), - PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), - PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), - PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), - - PINMUX_IPSR_GPSR(IP3_15_12, A12), - PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), - PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), - PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), - PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), - PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), - - PINMUX_IPSR_GPSR(IP3_19_16, A13), - PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), - PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), - PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), - PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), - PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), - - PINMUX_IPSR_GPSR(IP3_23_20, A14), - PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), - PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), - PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), - PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), - PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), - - PINMUX_IPSR_GPSR(IP3_27_24, A15), - PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), - PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), - PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), - PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), - PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), - - PINMUX_IPSR_GPSR(IP3_31_28, A16), - PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), - PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), - PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), - - /* IPSR4 */ - PINMUX_IPSR_GPSR(IP4_3_0, A17), - PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), - PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), - PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), - - PINMUX_IPSR_GPSR(IP4_7_4, A18), - PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), - PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), - PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), - - PINMUX_IPSR_GPSR(IP4_11_8, A19), - PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), - PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), - PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), - - PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), - PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), - - PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), - PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), - PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), - - PINMUX_IPSR_GPSR(IP4_23_20, BS_N), - PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), - PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP4_23_20, SCK3), - PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), - PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), - PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), - PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), - - PINMUX_IPSR_GPSR(IP4_27_24, RD_N), - PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), - PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), - PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), - PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), - PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), - - PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), - PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), - PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), - PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), - PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), - PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), - - /* IPSR5 */ - PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), - PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), - PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), - PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), - PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), - PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), - - PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), - PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), - PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), - PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), - PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), - PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), - PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), - - PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), - PINMUX_IPSR_GPSR(IP5_11_8, QCLK), - PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), - PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), - - PINMUX_IPSR_GPSR(IP5_15_12, D0), - PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), - PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), - PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), - PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), - - PINMUX_IPSR_GPSR(IP5_19_16, D1), - PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), - PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), - PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), - PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), - - PINMUX_IPSR_GPSR(IP5_23_20, D2), - PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), - PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), - PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), - - PINMUX_IPSR_GPSR(IP5_27_24, D3), - PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), - PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), - PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), - - PINMUX_IPSR_GPSR(IP5_31_28, D4), - PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), - PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), - - /* IPSR6 */ - PINMUX_IPSR_GPSR(IP6_3_0, D5), - PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), - PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), - - PINMUX_IPSR_GPSR(IP6_7_4, D6), - PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), - PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), - - PINMUX_IPSR_GPSR(IP6_11_8, D7), - PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), - PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), - - PINMUX_IPSR_GPSR(IP6_15_12, D8), - PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), - PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), - PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), - - PINMUX_IPSR_GPSR(IP6_19_16, D9), - PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), - PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), - - PINMUX_IPSR_GPSR(IP6_23_20, D10), - PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), - PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), - PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), - PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), - PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), - - PINMUX_IPSR_GPSR(IP6_27_24, D11), - PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), - PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), - PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), - PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), - PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), - - PINMUX_IPSR_GPSR(IP6_31_28, D12), - PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), - PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), - - /* IPSR7 */ - PINMUX_IPSR_GPSR(IP7_3_0, D13), - PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), - PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), - PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), - - PINMUX_IPSR_GPSR(IP7_7_4, D14), - PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), - PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), - PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), - PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), - PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), - - PINMUX_IPSR_GPSR(IP7_11_8, D15), - PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), - PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), - PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), - PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), - PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), - PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), - - PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), - - PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), - PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), - - PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), - PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), - - PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), - PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), - - PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), - PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), - - /* IPSR8 */ - PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), - PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), - - PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), - PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), - PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), - - PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), - PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), - - PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), - PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), - PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), - - PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), - PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), - PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), - PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), - - PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), - PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), - PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), - PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), - - PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), - PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), - PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), - PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), - - PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), - PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), - PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), - PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), - - /* IPSR9 */ - PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), - - PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0), - - PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1), - - PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2), - - PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3), - - PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS), - PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1), - - PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4), - PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), - - PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5), - PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0), - - /* IPSR10 */ - PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6), - PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD), - - PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7), - PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP), - - PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1), - PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0), - - PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), - - PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), - PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1), - - PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), - PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1), - - PINMUX_IPSR_GPSR(IP10_27_24, SCK0), - PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), - PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), - PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), - PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2), - - PINMUX_IPSR_GPSR(IP10_31_28, RX0), - PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), - - /* IPSR11 */ - PINMUX_IPSR_GPSR(IP11_3_0, TX0), - PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), - - PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N), - PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), - PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), - PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), - PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), - PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), - - PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N), - PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0), - PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), - PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), - PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1), - - PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0), - PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2), - - PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0), - PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2), - - PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N), - PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2), - PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), - PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), - PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), - - PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), - PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), - PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2), - PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1), - PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0), - - PINMUX_IPSR_GPSR(IP11_31_28, SCK2), - PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1), - PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2), - PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), - PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1), - PINMUX_IPSR_GPSR(IP11_31_28, ADICLK), - - /* IPSR12 */ - PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0), - PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1), - PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0), - PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2), - PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1), - - PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0), - PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1), - PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0), - PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2), - PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1), - - PINMUX_IPSR_GPSR(IP12_11_8, HSCK0), - PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0), - PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2), - - PINMUX_IPSR_GPSR(IP12_15_12, HRX0), - PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2), - - PINMUX_IPSR_GPSR(IP12_19_16, HTX0), - PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2), - - PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N), - PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2), - PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0), - - PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N), - PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0), - - PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), - PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0), - - /* IPSR13 */ - PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), - PINMUX_IPSR_GPSR(IP13_3_0, RX5), - PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2), - PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), - PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0), - PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1), - - PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), - PINMUX_IPSR_GPSR(IP13_7_4, TX5), - PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0), - PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), - PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3), - PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), - - PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK), - PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), - PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1), - - PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG), - PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), - PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1), - - PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT), - PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), - - PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239), - PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), - - PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239), - PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), - - PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0), - PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), - - /* IPSR14 */ - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0), - - PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), - - PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349), - PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), - - PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349), - PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), - PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), - - PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3), - PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0), - PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0), - PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0), - - PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4), - PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0), - PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0), - PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0), - - PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4), - PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0), - PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0), - PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0), - - PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4), - PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0), - PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), - PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0), - PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0), - - /* IPSR15 */ - PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6), - PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN), - PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3), - - PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6), - PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC), - PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3), - - PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6), - PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), - PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0), - - PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78), - PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0), - PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0), - PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0), - - PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78), - PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0), - PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0), - PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0), - - PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7), - PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0), - PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0), - PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0), - PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0), - - PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8), - PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), - PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0), - PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0), - - PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1), - PINMUX_IPSR_GPSR(IP15_31_28, SCK1), - PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_GPSR(IP15_31_28, SCK5), - - /* IPSR16 */ - PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), - - PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), - PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), - PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0), - PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0), - - PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN), - PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2), - PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), - PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1), - PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1), - - PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC), - PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2), - PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3), - PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1), - - PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN), - PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2), - PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4), - PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1), - PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1), - PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), - - PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC), - PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), - PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0), - PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4), - PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1), - PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1), - PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1), - - PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN), - PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), - PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), - PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0), - - PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC), - PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), - PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1), - PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1), - PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1), - - /* IPSR17 */ - PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN), - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4), - PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1), - PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2), - - PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1), - PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1), - PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), - PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), - PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), - PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3), - -/* - * Static pins can not be muxed between different functions but - * still need mark entries in the pinmux list. Add each static - * pin to the list without an associated function. The sh-pfc - * core will do the right thing and skip trying to mux the pin - * while still applying configuration to it. - */ -#define FM(x) PINMUX_DATA(x##_MARK, 0), - PINMUX_STATIC -#undef FM -}; - -/* - * Pins not associated with a GPIO port. - */ -enum { - GP_ASSIGN_LAST(), - NOGP_ALL(), -}; - -static const struct sh_pfc_pin pinmux_pins[] = { - PINMUX_GPIO_GP_ALL(), - PINMUX_NOGP_ALL(), -}; - -/* - AUDIO CLOCK ------------------------------------------------------------ */ -static const unsigned int audio_clk_a_a_pins[] = { - /* CLK A */ - RCAR_GP_PIN(6, 22), -}; -static const unsigned int audio_clk_a_a_mux[] = { - AUDIO_CLKA_A_MARK, -}; -static const unsigned int audio_clk_a_b_pins[] = { - /* CLK A */ - RCAR_GP_PIN(5, 4), -}; -static const unsigned int audio_clk_a_b_mux[] = { - AUDIO_CLKA_B_MARK, -}; -static const unsigned int audio_clk_a_c_pins[] = { - /* CLK A */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int audio_clk_a_c_mux[] = { - AUDIO_CLKA_C_MARK, -}; -static const unsigned int audio_clk_b_a_pins[] = { - /* CLK B */ - RCAR_GP_PIN(5, 12), -}; -static const unsigned int audio_clk_b_a_mux[] = { - AUDIO_CLKB_A_MARK, -}; -static const unsigned int audio_clk_b_b_pins[] = { - /* CLK B */ - RCAR_GP_PIN(6, 23), -}; -static const unsigned int audio_clk_b_b_mux[] = { - AUDIO_CLKB_B_MARK, -}; -static const unsigned int audio_clk_c_a_pins[] = { - /* CLK C */ - RCAR_GP_PIN(5, 21), -}; -static const unsigned int audio_clk_c_a_mux[] = { - AUDIO_CLKC_A_MARK, -}; -static const unsigned int audio_clk_c_b_pins[] = { - /* CLK C */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int audio_clk_c_b_mux[] = { - AUDIO_CLKC_B_MARK, -}; -static const unsigned int audio_clkout_a_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(5, 18), -}; -static const unsigned int audio_clkout_a_mux[] = { - AUDIO_CLKOUT_A_MARK, -}; -static const unsigned int audio_clkout_b_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(6, 28), -}; -static const unsigned int audio_clkout_b_mux[] = { - AUDIO_CLKOUT_B_MARK, -}; -static const unsigned int audio_clkout_c_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(5, 3), -}; -static const unsigned int audio_clkout_c_mux[] = { - AUDIO_CLKOUT_C_MARK, -}; -static const unsigned int audio_clkout_d_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(5, 21), -}; -static const unsigned int audio_clkout_d_mux[] = { - AUDIO_CLKOUT_D_MARK, -}; -static const unsigned int audio_clkout1_a_pins[] = { - /* CLKOUT1 */ - RCAR_GP_PIN(5, 15), -}; -static const unsigned int audio_clkout1_a_mux[] = { - AUDIO_CLKOUT1_A_MARK, -}; -static const unsigned int audio_clkout1_b_pins[] = { - /* CLKOUT1 */ - RCAR_GP_PIN(6, 29), -}; -static const unsigned int audio_clkout1_b_mux[] = { - AUDIO_CLKOUT1_B_MARK, -}; -static const unsigned int audio_clkout2_a_pins[] = { - /* CLKOUT2 */ - RCAR_GP_PIN(5, 16), -}; -static const unsigned int audio_clkout2_a_mux[] = { - AUDIO_CLKOUT2_A_MARK, -}; -static const unsigned int audio_clkout2_b_pins[] = { - /* CLKOUT2 */ - RCAR_GP_PIN(6, 30), -}; -static const unsigned int audio_clkout2_b_mux[] = { - AUDIO_CLKOUT2_B_MARK, -}; - -static const unsigned int audio_clkout3_a_pins[] = { - /* CLKOUT3 */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int audio_clkout3_a_mux[] = { - AUDIO_CLKOUT3_A_MARK, -}; -static const unsigned int audio_clkout3_b_pins[] = { - /* CLKOUT3 */ - RCAR_GP_PIN(6, 31), -}; -static const unsigned int audio_clkout3_b_mux[] = { - AUDIO_CLKOUT3_B_MARK, -}; - -/* - EtherAVB --------------------------------------------------------------- */ -static const unsigned int avb_link_pins[] = { - /* AVB_LINK */ - RCAR_GP_PIN(2, 12), -}; -static const unsigned int avb_link_mux[] = { - AVB_LINK_MARK, -}; -static const unsigned int avb_magic_pins[] = { - /* AVB_MAGIC_ */ - RCAR_GP_PIN(2, 10), -}; -static const unsigned int avb_magic_mux[] = { - AVB_MAGIC_MARK, -}; -static const unsigned int avb_phy_int_pins[] = { - /* AVB_PHY_INT */ - RCAR_GP_PIN(2, 11), -}; -static const unsigned int avb_phy_int_mux[] = { - AVB_PHY_INT_MARK, -}; -static const unsigned int avb_mdio_pins[] = { - /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, -}; -static const unsigned int avb_mdio_mux[] = { - AVB_MDC_MARK, AVB_MDIO_MARK, -}; -static const unsigned int avb_mii_pins[] = { - /* - * AVB_TX_CTL, AVB_TXC, AVB_TD0, - * AVB_TD1, AVB_TD2, AVB_TD3, - * AVB_RX_CTL, AVB_RXC, AVB_RD0, - * AVB_RD1, AVB_RD2, AVB_RD3, - * AVB_TXCREFCLK - */ - PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, - PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, - PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, - PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, - PIN_AVB_TXCREFCLK, -}; -static const unsigned int avb_mii_mux[] = { - AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, - AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, - AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, - AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, - AVB_TXCREFCLK_MARK, -}; -static const unsigned int avb_avtp_pps_pins[] = { - /* AVB_AVTP_PPS */ - RCAR_GP_PIN(2, 6), -}; -static const unsigned int avb_avtp_pps_mux[] = { - AVB_AVTP_PPS_MARK, -}; -static const unsigned int avb_avtp_match_a_pins[] = { - /* AVB_AVTP_MATCH_A */ - RCAR_GP_PIN(2, 13), -}; -static const unsigned int avb_avtp_match_a_mux[] = { - AVB_AVTP_MATCH_A_MARK, -}; -static const unsigned int avb_avtp_capture_a_pins[] = { - /* AVB_AVTP_CAPTURE_A */ - RCAR_GP_PIN(2, 14), -}; -static const unsigned int avb_avtp_capture_a_mux[] = { - AVB_AVTP_CAPTURE_A_MARK, -}; -static const unsigned int avb_avtp_match_b_pins[] = { - /* AVB_AVTP_MATCH_B */ - RCAR_GP_PIN(1, 8), -}; -static const unsigned int avb_avtp_match_b_mux[] = { - AVB_AVTP_MATCH_B_MARK, -}; -static const unsigned int avb_avtp_capture_b_pins[] = { - /* AVB_AVTP_CAPTURE_B */ - RCAR_GP_PIN(1, 11), -}; -static const unsigned int avb_avtp_capture_b_mux[] = { - AVB_AVTP_CAPTURE_B_MARK, -}; - -/* - CAN ------------------------------------------------------------------ */ -static const unsigned int can0_data_a_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), -}; -static const unsigned int can0_data_a_mux[] = { - CAN0_TX_A_MARK, CAN0_RX_A_MARK, -}; -static const unsigned int can0_data_b_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), -}; -static const unsigned int can0_data_b_mux[] = { - CAN0_TX_B_MARK, CAN0_RX_B_MARK, -}; -static const unsigned int can1_data_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), -}; -static const unsigned int can1_data_mux[] = { - CAN1_TX_MARK, CAN1_RX_MARK, -}; - -/* - CAN Clock -------------------------------------------------------------- */ -static const unsigned int can_clk_pins[] = { - /* CLK */ - RCAR_GP_PIN(1, 25), -}; -static const unsigned int can_clk_mux[] = { - CAN_CLK_MARK, -}; - -/* - CAN FD --------------------------------------------------------------- */ -static const unsigned int canfd0_data_a_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), -}; -static const unsigned int canfd0_data_a_mux[] = { - CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, -}; -static const unsigned int canfd0_data_b_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), -}; -static const unsigned int canfd0_data_b_mux[] = { - CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, -}; -static const unsigned int canfd1_data_pins[] = { - /* TX, RX */ - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), -}; -static const unsigned int canfd1_data_mux[] = { - CANFD1_TX_MARK, CANFD1_RX_MARK, -}; - -/* - DRIF0 --------------------------------------------------------------- */ -static const unsigned int drif0_ctrl_a_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), -}; -static const unsigned int drif0_ctrl_a_mux[] = { - RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, -}; -static const unsigned int drif0_data0_a_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int drif0_data0_a_mux[] = { - RIF0_D0_A_MARK, -}; -static const unsigned int drif0_data1_a_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 7), -}; -static const unsigned int drif0_data1_a_mux[] = { - RIF0_D1_A_MARK, -}; -static const unsigned int drif0_ctrl_b_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), -}; -static const unsigned int drif0_ctrl_b_mux[] = { - RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, -}; -static const unsigned int drif0_data0_b_pins[] = { - /* D0 */ - RCAR_GP_PIN(5, 1), -}; -static const unsigned int drif0_data0_b_mux[] = { - RIF0_D0_B_MARK, -}; -static const unsigned int drif0_data1_b_pins[] = { - /* D1 */ - RCAR_GP_PIN(5, 2), -}; -static const unsigned int drif0_data1_b_mux[] = { - RIF0_D1_B_MARK, -}; -static const unsigned int drif0_ctrl_c_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), -}; -static const unsigned int drif0_ctrl_c_mux[] = { - RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, -}; -static const unsigned int drif0_data0_c_pins[] = { - /* D0 */ - RCAR_GP_PIN(5, 13), -}; -static const unsigned int drif0_data0_c_mux[] = { - RIF0_D0_C_MARK, -}; -static const unsigned int drif0_data1_c_pins[] = { - /* D1 */ - RCAR_GP_PIN(5, 14), -}; -static const unsigned int drif0_data1_c_mux[] = { - RIF0_D1_C_MARK, -}; -/* - DRIF1 --------------------------------------------------------------- */ -static const unsigned int drif1_ctrl_a_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), -}; -static const unsigned int drif1_ctrl_a_mux[] = { - RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, -}; -static const unsigned int drif1_data0_a_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 19), -}; -static const unsigned int drif1_data0_a_mux[] = { - RIF1_D0_A_MARK, -}; -static const unsigned int drif1_data1_a_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 20), -}; -static const unsigned int drif1_data1_a_mux[] = { - RIF1_D1_A_MARK, -}; -static const unsigned int drif1_ctrl_b_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), -}; -static const unsigned int drif1_ctrl_b_mux[] = { - RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, -}; -static const unsigned int drif1_data0_b_pins[] = { - /* D0 */ - RCAR_GP_PIN(5, 7), -}; -static const unsigned int drif1_data0_b_mux[] = { - RIF1_D0_B_MARK, -}; -static const unsigned int drif1_data1_b_pins[] = { - /* D1 */ - RCAR_GP_PIN(5, 8), -}; -static const unsigned int drif1_data1_b_mux[] = { - RIF1_D1_B_MARK, -}; -static const unsigned int drif1_ctrl_c_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), -}; -static const unsigned int drif1_ctrl_c_mux[] = { - RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, -}; -static const unsigned int drif1_data0_c_pins[] = { - /* D0 */ - RCAR_GP_PIN(5, 6), -}; -static const unsigned int drif1_data0_c_mux[] = { - RIF1_D0_C_MARK, -}; -static const unsigned int drif1_data1_c_pins[] = { - /* D1 */ - RCAR_GP_PIN(5, 10), -}; -static const unsigned int drif1_data1_c_mux[] = { - RIF1_D1_C_MARK, -}; -/* - DRIF2 --------------------------------------------------------------- */ -static const unsigned int drif2_ctrl_a_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), -}; -static const unsigned int drif2_ctrl_a_mux[] = { - RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, -}; -static const unsigned int drif2_data0_a_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 7), -}; -static const unsigned int drif2_data0_a_mux[] = { - RIF2_D0_A_MARK, -}; -static const unsigned int drif2_data1_a_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int drif2_data1_a_mux[] = { - RIF2_D1_A_MARK, -}; -static const unsigned int drif2_ctrl_b_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), -}; -static const unsigned int drif2_ctrl_b_mux[] = { - RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, -}; -static const unsigned int drif2_data0_b_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 30), -}; -static const unsigned int drif2_data0_b_mux[] = { - RIF2_D0_B_MARK, -}; -static const unsigned int drif2_data1_b_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 31), -}; -static const unsigned int drif2_data1_b_mux[] = { - RIF2_D1_B_MARK, -}; -/* - DRIF3 --------------------------------------------------------------- */ -static const unsigned int drif3_ctrl_a_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), -}; -static const unsigned int drif3_ctrl_a_mux[] = { - RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, -}; -static const unsigned int drif3_data0_a_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 19), -}; -static const unsigned int drif3_data0_a_mux[] = { - RIF3_D0_A_MARK, -}; -static const unsigned int drif3_data1_a_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 20), -}; -static const unsigned int drif3_data1_a_mux[] = { - RIF3_D1_A_MARK, -}; -static const unsigned int drif3_ctrl_b_pins[] = { - /* CLK, SYNC */ - RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), -}; -static const unsigned int drif3_ctrl_b_mux[] = { - RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, -}; -static const unsigned int drif3_data0_b_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 28), -}; -static const unsigned int drif3_data0_b_mux[] = { - RIF3_D0_B_MARK, -}; -static const unsigned int drif3_data1_b_pins[] = { - /* D1 */ - RCAR_GP_PIN(6, 29), -}; -static const unsigned int drif3_data1_b_mux[] = { - RIF3_D1_B_MARK, -}; - -/* - DU --------------------------------------------------------------------- */ -static const unsigned int du_rgb666_pins[] = { - /* R[7:2], G[7:2], B[7:2] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), -}; -static const unsigned int du_rgb666_mux[] = { - DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, - DU_DR3_MARK, DU_DR2_MARK, - DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, - DU_DG3_MARK, DU_DG2_MARK, - DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, - DU_DB3_MARK, DU_DB2_MARK, -}; -static const unsigned int du_rgb888_pins[] = { - /* R[7:0], G[7:0], B[7:0] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), - RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), -}; -static const unsigned int du_rgb888_mux[] = { - DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, - DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, - DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, - DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, - DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, - DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, -}; -static const unsigned int du_clk_out_0_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(1, 27), -}; -static const unsigned int du_clk_out_0_mux[] = { - DU_DOTCLKOUT0_MARK -}; -static const unsigned int du_clk_out_1_pins[] = { - /* CLKOUT */ - RCAR_GP_PIN(2, 3), -}; -static const unsigned int du_clk_out_1_mux[] = { - DU_DOTCLKOUT1_MARK -}; -static const unsigned int du_sync_pins[] = { - /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), -}; -static const unsigned int du_sync_mux[] = { - DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK -}; -static const unsigned int du_oddf_pins[] = { - /* EXDISP/EXODDF/EXCDE */ - RCAR_GP_PIN(2, 2), -}; -static const unsigned int du_oddf_mux[] = { - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, -}; -static const unsigned int du_cde_pins[] = { - /* CDE */ - RCAR_GP_PIN(2, 0), -}; -static const unsigned int du_cde_mux[] = { - DU_CDE_MARK, -}; -static const unsigned int du_disp_pins[] = { - /* DISP */ - RCAR_GP_PIN(2, 1), -}; -static const unsigned int du_disp_mux[] = { - DU_DISP_MARK, -}; -/* - HSCIF0 ----------------------------------------------------------------- */ -static const unsigned int hscif0_data_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), -}; -static const unsigned int hscif0_data_mux[] = { - HRX0_MARK, HTX0_MARK, -}; -static const unsigned int hscif0_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 12), -}; -static const unsigned int hscif0_clk_mux[] = { - HSCK0_MARK, -}; -static const unsigned int hscif0_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), -}; -static const unsigned int hscif0_ctrl_mux[] = { - HRTS0_N_MARK, HCTS0_N_MARK, -}; -/* - HSCIF1 ----------------------------------------------------------------- */ -static const unsigned int hscif1_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), -}; -static const unsigned int hscif1_data_a_mux[] = { - HRX1_A_MARK, HTX1_A_MARK, -}; -static const unsigned int hscif1_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int hscif1_clk_a_mux[] = { - HSCK1_A_MARK, -}; -static const unsigned int hscif1_ctrl_a_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), -}; -static const unsigned int hscif1_ctrl_a_mux[] = { - HRTS1_N_A_MARK, HCTS1_N_A_MARK, -}; - -static const unsigned int hscif1_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int hscif1_data_b_mux[] = { - HRX1_B_MARK, HTX1_B_MARK, -}; -static const unsigned int hscif1_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int hscif1_clk_b_mux[] = { - HSCK1_B_MARK, -}; -static const unsigned int hscif1_ctrl_b_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), -}; -static const unsigned int hscif1_ctrl_b_mux[] = { - HRTS1_N_B_MARK, HCTS1_N_B_MARK, -}; -/* - HSCIF2 ----------------------------------------------------------------- */ -static const unsigned int hscif2_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), -}; -static const unsigned int hscif2_data_a_mux[] = { - HRX2_A_MARK, HTX2_A_MARK, -}; -static const unsigned int hscif2_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int hscif2_clk_a_mux[] = { - HSCK2_A_MARK, -}; -static const unsigned int hscif2_ctrl_a_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), -}; -static const unsigned int hscif2_ctrl_a_mux[] = { - HRTS2_N_A_MARK, HCTS2_N_A_MARK, -}; - -static const unsigned int hscif2_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), -}; -static const unsigned int hscif2_data_b_mux[] = { - HRX2_B_MARK, HTX2_B_MARK, -}; -static const unsigned int hscif2_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int hscif2_clk_b_mux[] = { - HSCK2_B_MARK, -}; -static const unsigned int hscif2_ctrl_b_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), -}; -static const unsigned int hscif2_ctrl_b_mux[] = { - HRTS2_N_B_MARK, HCTS2_N_B_MARK, -}; -/* - HSCIF3 ----------------------------------------------------------------- */ -static const unsigned int hscif3_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), -}; -static const unsigned int hscif3_data_a_mux[] = { - HRX3_A_MARK, HTX3_A_MARK, -}; -static const unsigned int hscif3_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 22), -}; -static const unsigned int hscif3_clk_mux[] = { - HSCK3_MARK, -}; -static const unsigned int hscif3_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), -}; -static const unsigned int hscif3_ctrl_mux[] = { - HRTS3_N_MARK, HCTS3_N_MARK, -}; - -static const unsigned int hscif3_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), -}; -static const unsigned int hscif3_data_b_mux[] = { - HRX3_B_MARK, HTX3_B_MARK, -}; -static const unsigned int hscif3_data_c_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), -}; -static const unsigned int hscif3_data_c_mux[] = { - HRX3_C_MARK, HTX3_C_MARK, -}; -static const unsigned int hscif3_data_d_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), -}; -static const unsigned int hscif3_data_d_mux[] = { - HRX3_D_MARK, HTX3_D_MARK, -}; -/* - HSCIF4 ----------------------------------------------------------------- */ -static const unsigned int hscif4_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), -}; -static const unsigned int hscif4_data_a_mux[] = { - HRX4_A_MARK, HTX4_A_MARK, -}; -static const unsigned int hscif4_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 11), -}; -static const unsigned int hscif4_clk_mux[] = { - HSCK4_MARK, -}; -static const unsigned int hscif4_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), -}; -static const unsigned int hscif4_ctrl_mux[] = { - HRTS4_N_MARK, HCTS4_N_MARK, -}; - -static const unsigned int hscif4_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), -}; -static const unsigned int hscif4_data_b_mux[] = { - HRX4_B_MARK, HTX4_B_MARK, -}; - -/* - I2C -------------------------------------------------------------------- */ -static const unsigned int i2c0_pins[] = { - /* SCL, SDA */ - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), -}; - -static const unsigned int i2c0_mux[] = { - SCL0_MARK, SDA0_MARK, -}; - -static const unsigned int i2c1_a_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), -}; -static const unsigned int i2c1_a_mux[] = { - SDA1_A_MARK, SCL1_A_MARK, -}; -static const unsigned int i2c1_b_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), -}; -static const unsigned int i2c1_b_mux[] = { - SDA1_B_MARK, SCL1_B_MARK, -}; -static const unsigned int i2c2_a_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), -}; -static const unsigned int i2c2_a_mux[] = { - SDA2_A_MARK, SCL2_A_MARK, -}; -static const unsigned int i2c2_b_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), -}; -static const unsigned int i2c2_b_mux[] = { - SDA2_B_MARK, SCL2_B_MARK, -}; - -static const unsigned int i2c3_pins[] = { - /* SCL, SDA */ - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), -}; - -static const unsigned int i2c3_mux[] = { - SCL3_MARK, SDA3_MARK, -}; - -static const unsigned int i2c5_pins[] = { - /* SCL, SDA */ - RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), -}; - -static const unsigned int i2c5_mux[] = { - SCL5_MARK, SDA5_MARK, -}; - -static const unsigned int i2c6_a_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), -}; -static const unsigned int i2c6_a_mux[] = { - SDA6_A_MARK, SCL6_A_MARK, -}; -static const unsigned int i2c6_b_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), -}; -static const unsigned int i2c6_b_mux[] = { - SDA6_B_MARK, SCL6_B_MARK, -}; -static const unsigned int i2c6_c_pins[] = { - /* SDA, SCL */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), -}; -static const unsigned int i2c6_c_mux[] = { - SDA6_C_MARK, SCL6_C_MARK, -}; - -/* - INTC-EX ---------------------------------------------------------------- */ -static const unsigned int intc_ex_irq0_pins[] = { - /* IRQ0 */ - RCAR_GP_PIN(2, 0), -}; -static const unsigned int intc_ex_irq0_mux[] = { - IRQ0_MARK, -}; -static const unsigned int intc_ex_irq1_pins[] = { - /* IRQ1 */ - RCAR_GP_PIN(2, 1), -}; -static const unsigned int intc_ex_irq1_mux[] = { - IRQ1_MARK, -}; -static const unsigned int intc_ex_irq2_pins[] = { - /* IRQ2 */ - RCAR_GP_PIN(2, 2), -}; -static const unsigned int intc_ex_irq2_mux[] = { - IRQ2_MARK, -}; -static const unsigned int intc_ex_irq3_pins[] = { - /* IRQ3 */ - RCAR_GP_PIN(2, 3), -}; -static const unsigned int intc_ex_irq3_mux[] = { - IRQ3_MARK, -}; -static const unsigned int intc_ex_irq4_pins[] = { - /* IRQ4 */ - RCAR_GP_PIN(2, 4), -}; -static const unsigned int intc_ex_irq4_mux[] = { - IRQ4_MARK, -}; -static const unsigned int intc_ex_irq5_pins[] = { - /* IRQ5 */ - RCAR_GP_PIN(2, 5), -}; -static const unsigned int intc_ex_irq5_mux[] = { - IRQ5_MARK, -}; - -/* - MLB+ ------------------------------------------------------------------- */ -static const unsigned int mlb_3pin_pins[] = { - RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), -}; -static const unsigned int mlb_3pin_mux[] = { - MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, -}; - -/* - MSIOF0 ----------------------------------------------------------------- */ -static const unsigned int msiof0_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 17), -}; -static const unsigned int msiof0_clk_mux[] = { - MSIOF0_SCK_MARK, -}; -static const unsigned int msiof0_sync_pins[] = { - /* SYNC */ - RCAR_GP_PIN(5, 18), -}; -static const unsigned int msiof0_sync_mux[] = { - MSIOF0_SYNC_MARK, -}; -static const unsigned int msiof0_ss1_pins[] = { - /* SS1 */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int msiof0_ss1_mux[] = { - MSIOF0_SS1_MARK, -}; -static const unsigned int msiof0_ss2_pins[] = { - /* SS2 */ - RCAR_GP_PIN(5, 21), -}; -static const unsigned int msiof0_ss2_mux[] = { - MSIOF0_SS2_MARK, -}; -static const unsigned int msiof0_txd_pins[] = { - /* TXD */ - RCAR_GP_PIN(5, 20), -}; -static const unsigned int msiof0_txd_mux[] = { - MSIOF0_TXD_MARK, -}; -static const unsigned int msiof0_rxd_pins[] = { - /* RXD */ - RCAR_GP_PIN(5, 22), -}; -static const unsigned int msiof0_rxd_mux[] = { - MSIOF0_RXD_MARK, -}; -/* - MSIOF1 ----------------------------------------------------------------- */ -static const unsigned int msiof1_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 8), -}; -static const unsigned int msiof1_clk_a_mux[] = { - MSIOF1_SCK_A_MARK, -}; -static const unsigned int msiof1_sync_a_pins[] = { - /* SYNC */ - RCAR_GP_PIN(6, 9), -}; -static const unsigned int msiof1_sync_a_mux[] = { - MSIOF1_SYNC_A_MARK, -}; -static const unsigned int msiof1_ss1_a_pins[] = { - /* SS1 */ - RCAR_GP_PIN(6, 5), -}; -static const unsigned int msiof1_ss1_a_mux[] = { - MSIOF1_SS1_A_MARK, -}; -static const unsigned int msiof1_ss2_a_pins[] = { - /* SS2 */ - RCAR_GP_PIN(6, 6), -}; -static const unsigned int msiof1_ss2_a_mux[] = { - MSIOF1_SS2_A_MARK, -}; -static const unsigned int msiof1_txd_a_pins[] = { - /* TXD */ - RCAR_GP_PIN(6, 7), -}; -static const unsigned int msiof1_txd_a_mux[] = { - MSIOF1_TXD_A_MARK, -}; -static const unsigned int msiof1_rxd_a_pins[] = { - /* RXD */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int msiof1_rxd_a_mux[] = { - MSIOF1_RXD_A_MARK, -}; -static const unsigned int msiof1_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 9), -}; -static const unsigned int msiof1_clk_b_mux[] = { - MSIOF1_SCK_B_MARK, -}; -static const unsigned int msiof1_sync_b_pins[] = { - /* SYNC */ - RCAR_GP_PIN(5, 3), -}; -static const unsigned int msiof1_sync_b_mux[] = { - MSIOF1_SYNC_B_MARK, -}; -static const unsigned int msiof1_ss1_b_pins[] = { - /* SS1 */ - RCAR_GP_PIN(5, 4), -}; -static const unsigned int msiof1_ss1_b_mux[] = { - MSIOF1_SS1_B_MARK, -}; -static const unsigned int msiof1_ss2_b_pins[] = { - /* SS2 */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int msiof1_ss2_b_mux[] = { - MSIOF1_SS2_B_MARK, -}; -static const unsigned int msiof1_txd_b_pins[] = { - /* TXD */ - RCAR_GP_PIN(5, 8), -}; -static const unsigned int msiof1_txd_b_mux[] = { - MSIOF1_TXD_B_MARK, -}; -static const unsigned int msiof1_rxd_b_pins[] = { - /* RXD */ - RCAR_GP_PIN(5, 7), -}; -static const unsigned int msiof1_rxd_b_mux[] = { - MSIOF1_RXD_B_MARK, -}; -static const unsigned int msiof1_clk_c_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 17), -}; -static const unsigned int msiof1_clk_c_mux[] = { - MSIOF1_SCK_C_MARK, -}; -static const unsigned int msiof1_sync_c_pins[] = { - /* SYNC */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int msiof1_sync_c_mux[] = { - MSIOF1_SYNC_C_MARK, -}; -static const unsigned int msiof1_ss1_c_pins[] = { - /* SS1 */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int msiof1_ss1_c_mux[] = { - MSIOF1_SS1_C_MARK, -}; -static const unsigned int msiof1_ss2_c_pins[] = { - /* SS2 */ - RCAR_GP_PIN(6, 27), -}; -static const unsigned int msiof1_ss2_c_mux[] = { - MSIOF1_SS2_C_MARK, -}; -static const unsigned int msiof1_txd_c_pins[] = { - /* TXD */ - RCAR_GP_PIN(6, 20), -}; -static const unsigned int msiof1_txd_c_mux[] = { - MSIOF1_TXD_C_MARK, -}; -static const unsigned int msiof1_rxd_c_pins[] = { - /* RXD */ - RCAR_GP_PIN(6, 19), -}; -static const unsigned int msiof1_rxd_c_mux[] = { - MSIOF1_RXD_C_MARK, -}; -static const unsigned int msiof1_clk_d_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 12), -}; -static const unsigned int msiof1_clk_d_mux[] = { - MSIOF1_SCK_D_MARK, -}; -static const unsigned int msiof1_sync_d_pins[] = { - /* SYNC */ - RCAR_GP_PIN(5, 15), -}; -static const unsigned int msiof1_sync_d_mux[] = { - MSIOF1_SYNC_D_MARK, -}; -static const unsigned int msiof1_ss1_d_pins[] = { - /* SS1 */ - RCAR_GP_PIN(5, 16), -}; -static const unsigned int msiof1_ss1_d_mux[] = { - MSIOF1_SS1_D_MARK, -}; -static const unsigned int msiof1_ss2_d_pins[] = { - /* SS2 */ - RCAR_GP_PIN(5, 21), -}; -static const unsigned int msiof1_ss2_d_mux[] = { - MSIOF1_SS2_D_MARK, -}; -static const unsigned int msiof1_txd_d_pins[] = { - /* TXD */ - RCAR_GP_PIN(5, 14), -}; -static const unsigned int msiof1_txd_d_mux[] = { - MSIOF1_TXD_D_MARK, -}; -static const unsigned int msiof1_rxd_d_pins[] = { - /* RXD */ - RCAR_GP_PIN(5, 13), -}; -static const unsigned int msiof1_rxd_d_mux[] = { - MSIOF1_RXD_D_MARK, -}; -static const unsigned int msiof1_clk_e_pins[] = { - /* SCK */ - RCAR_GP_PIN(3, 0), -}; -static const unsigned int msiof1_clk_e_mux[] = { - MSIOF1_SCK_E_MARK, -}; -static const unsigned int msiof1_sync_e_pins[] = { - /* SYNC */ - RCAR_GP_PIN(3, 1), -}; -static const unsigned int msiof1_sync_e_mux[] = { - MSIOF1_SYNC_E_MARK, -}; -static const unsigned int msiof1_ss1_e_pins[] = { - /* SS1 */ - RCAR_GP_PIN(3, 4), -}; -static const unsigned int msiof1_ss1_e_mux[] = { - MSIOF1_SS1_E_MARK, -}; -static const unsigned int msiof1_ss2_e_pins[] = { - /* SS2 */ - RCAR_GP_PIN(3, 5), -}; -static const unsigned int msiof1_ss2_e_mux[] = { - MSIOF1_SS2_E_MARK, -}; -static const unsigned int msiof1_txd_e_pins[] = { - /* TXD */ - RCAR_GP_PIN(3, 3), -}; -static const unsigned int msiof1_txd_e_mux[] = { - MSIOF1_TXD_E_MARK, -}; -static const unsigned int msiof1_rxd_e_pins[] = { - /* RXD */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int msiof1_rxd_e_mux[] = { - MSIOF1_RXD_E_MARK, -}; -static const unsigned int msiof1_clk_f_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 23), -}; -static const unsigned int msiof1_clk_f_mux[] = { - MSIOF1_SCK_F_MARK, -}; -static const unsigned int msiof1_sync_f_pins[] = { - /* SYNC */ - RCAR_GP_PIN(5, 24), -}; -static const unsigned int msiof1_sync_f_mux[] = { - MSIOF1_SYNC_F_MARK, -}; -static const unsigned int msiof1_ss1_f_pins[] = { - /* SS1 */ - RCAR_GP_PIN(6, 1), -}; -static const unsigned int msiof1_ss1_f_mux[] = { - MSIOF1_SS1_F_MARK, -}; -static const unsigned int msiof1_ss2_f_pins[] = { - /* SS2 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int msiof1_ss2_f_mux[] = { - MSIOF1_SS2_F_MARK, -}; -static const unsigned int msiof1_txd_f_pins[] = { - /* TXD */ - RCAR_GP_PIN(6, 0), -}; -static const unsigned int msiof1_txd_f_mux[] = { - MSIOF1_TXD_F_MARK, -}; -static const unsigned int msiof1_rxd_f_pins[] = { - /* RXD */ - RCAR_GP_PIN(5, 25), -}; -static const unsigned int msiof1_rxd_f_mux[] = { - MSIOF1_RXD_F_MARK, -}; -static const unsigned int msiof1_clk_g_pins[] = { - /* SCK */ - RCAR_GP_PIN(3, 6), -}; -static const unsigned int msiof1_clk_g_mux[] = { - MSIOF1_SCK_G_MARK, -}; -static const unsigned int msiof1_sync_g_pins[] = { - /* SYNC */ - RCAR_GP_PIN(3, 7), -}; -static const unsigned int msiof1_sync_g_mux[] = { - MSIOF1_SYNC_G_MARK, -}; -static const unsigned int msiof1_ss1_g_pins[] = { - /* SS1 */ - RCAR_GP_PIN(3, 10), -}; -static const unsigned int msiof1_ss1_g_mux[] = { - MSIOF1_SS1_G_MARK, -}; -static const unsigned int msiof1_ss2_g_pins[] = { - /* SS2 */ - RCAR_GP_PIN(3, 11), -}; -static const unsigned int msiof1_ss2_g_mux[] = { - MSIOF1_SS2_G_MARK, -}; -static const unsigned int msiof1_txd_g_pins[] = { - /* TXD */ - RCAR_GP_PIN(3, 9), -}; -static const unsigned int msiof1_txd_g_mux[] = { - MSIOF1_TXD_G_MARK, -}; -static const unsigned int msiof1_rxd_g_pins[] = { - /* RXD */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int msiof1_rxd_g_mux[] = { - MSIOF1_RXD_G_MARK, -}; -/* - MSIOF2 ----------------------------------------------------------------- */ -static const unsigned int msiof2_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 9), -}; -static const unsigned int msiof2_clk_a_mux[] = { - MSIOF2_SCK_A_MARK, -}; -static const unsigned int msiof2_sync_a_pins[] = { - /* SYNC */ - RCAR_GP_PIN(1, 8), -}; -static const unsigned int msiof2_sync_a_mux[] = { - MSIOF2_SYNC_A_MARK, -}; -static const unsigned int msiof2_ss1_a_pins[] = { - /* SS1 */ - RCAR_GP_PIN(1, 6), -}; -static const unsigned int msiof2_ss1_a_mux[] = { - MSIOF2_SS1_A_MARK, -}; -static const unsigned int msiof2_ss2_a_pins[] = { - /* SS2 */ - RCAR_GP_PIN(1, 7), -}; -static const unsigned int msiof2_ss2_a_mux[] = { - MSIOF2_SS2_A_MARK, -}; -static const unsigned int msiof2_txd_a_pins[] = { - /* TXD */ - RCAR_GP_PIN(1, 11), -}; -static const unsigned int msiof2_txd_a_mux[] = { - MSIOF2_TXD_A_MARK, -}; -static const unsigned int msiof2_rxd_a_pins[] = { - /* RXD */ - RCAR_GP_PIN(1, 10), -}; -static const unsigned int msiof2_rxd_a_mux[] = { - MSIOF2_RXD_A_MARK, -}; -static const unsigned int msiof2_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(0, 4), -}; -static const unsigned int msiof2_clk_b_mux[] = { - MSIOF2_SCK_B_MARK, -}; -static const unsigned int msiof2_sync_b_pins[] = { - /* SYNC */ - RCAR_GP_PIN(0, 5), -}; -static const unsigned int msiof2_sync_b_mux[] = { - MSIOF2_SYNC_B_MARK, -}; -static const unsigned int msiof2_ss1_b_pins[] = { - /* SS1 */ - RCAR_GP_PIN(0, 0), -}; -static const unsigned int msiof2_ss1_b_mux[] = { - MSIOF2_SS1_B_MARK, -}; -static const unsigned int msiof2_ss2_b_pins[] = { - /* SS2 */ - RCAR_GP_PIN(0, 1), -}; -static const unsigned int msiof2_ss2_b_mux[] = { - MSIOF2_SS2_B_MARK, -}; -static const unsigned int msiof2_txd_b_pins[] = { - /* TXD */ - RCAR_GP_PIN(0, 7), -}; -static const unsigned int msiof2_txd_b_mux[] = { - MSIOF2_TXD_B_MARK, -}; -static const unsigned int msiof2_rxd_b_pins[] = { - /* RXD */ - RCAR_GP_PIN(0, 6), -}; -static const unsigned int msiof2_rxd_b_mux[] = { - MSIOF2_RXD_B_MARK, -}; -static const unsigned int msiof2_clk_c_pins[] = { - /* SCK */ - RCAR_GP_PIN(2, 12), -}; -static const unsigned int msiof2_clk_c_mux[] = { - MSIOF2_SCK_C_MARK, -}; -static const unsigned int msiof2_sync_c_pins[] = { - /* SYNC */ - RCAR_GP_PIN(2, 11), -}; -static const unsigned int msiof2_sync_c_mux[] = { - MSIOF2_SYNC_C_MARK, -}; -static const unsigned int msiof2_ss1_c_pins[] = { - /* SS1 */ - RCAR_GP_PIN(2, 10), -}; -static const unsigned int msiof2_ss1_c_mux[] = { - MSIOF2_SS1_C_MARK, -}; -static const unsigned int msiof2_ss2_c_pins[] = { - /* SS2 */ - RCAR_GP_PIN(2, 9), -}; -static const unsigned int msiof2_ss2_c_mux[] = { - MSIOF2_SS2_C_MARK, -}; -static const unsigned int msiof2_txd_c_pins[] = { - /* TXD */ - RCAR_GP_PIN(2, 14), -}; -static const unsigned int msiof2_txd_c_mux[] = { - MSIOF2_TXD_C_MARK, -}; -static const unsigned int msiof2_rxd_c_pins[] = { - /* RXD */ - RCAR_GP_PIN(2, 13), -}; -static const unsigned int msiof2_rxd_c_mux[] = { - MSIOF2_RXD_C_MARK, -}; -static const unsigned int msiof2_clk_d_pins[] = { - /* SCK */ - RCAR_GP_PIN(0, 8), -}; -static const unsigned int msiof2_clk_d_mux[] = { - MSIOF2_SCK_D_MARK, -}; -static const unsigned int msiof2_sync_d_pins[] = { - /* SYNC */ - RCAR_GP_PIN(0, 9), -}; -static const unsigned int msiof2_sync_d_mux[] = { - MSIOF2_SYNC_D_MARK, -}; -static const unsigned int msiof2_ss1_d_pins[] = { - /* SS1 */ - RCAR_GP_PIN(0, 12), -}; -static const unsigned int msiof2_ss1_d_mux[] = { - MSIOF2_SS1_D_MARK, -}; -static const unsigned int msiof2_ss2_d_pins[] = { - /* SS2 */ - RCAR_GP_PIN(0, 13), -}; -static const unsigned int msiof2_ss2_d_mux[] = { - MSIOF2_SS2_D_MARK, -}; -static const unsigned int msiof2_txd_d_pins[] = { - /* TXD */ - RCAR_GP_PIN(0, 11), -}; -static const unsigned int msiof2_txd_d_mux[] = { - MSIOF2_TXD_D_MARK, -}; -static const unsigned int msiof2_rxd_d_pins[] = { - /* RXD */ - RCAR_GP_PIN(0, 10), -}; -static const unsigned int msiof2_rxd_d_mux[] = { - MSIOF2_RXD_D_MARK, -}; -/* - MSIOF3 ----------------------------------------------------------------- */ -static const unsigned int msiof3_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(0, 0), -}; -static const unsigned int msiof3_clk_a_mux[] = { - MSIOF3_SCK_A_MARK, -}; -static const unsigned int msiof3_sync_a_pins[] = { - /* SYNC */ - RCAR_GP_PIN(0, 1), -}; -static const unsigned int msiof3_sync_a_mux[] = { - MSIOF3_SYNC_A_MARK, -}; -static const unsigned int msiof3_ss1_a_pins[] = { - /* SS1 */ - RCAR_GP_PIN(0, 14), -}; -static const unsigned int msiof3_ss1_a_mux[] = { - MSIOF3_SS1_A_MARK, -}; -static const unsigned int msiof3_ss2_a_pins[] = { - /* SS2 */ - RCAR_GP_PIN(0, 15), -}; -static const unsigned int msiof3_ss2_a_mux[] = { - MSIOF3_SS2_A_MARK, -}; -static const unsigned int msiof3_txd_a_pins[] = { - /* TXD */ - RCAR_GP_PIN(0, 3), -}; -static const unsigned int msiof3_txd_a_mux[] = { - MSIOF3_TXD_A_MARK, -}; -static const unsigned int msiof3_rxd_a_pins[] = { - /* RXD */ - RCAR_GP_PIN(0, 2), -}; -static const unsigned int msiof3_rxd_a_mux[] = { - MSIOF3_RXD_A_MARK, -}; -static const unsigned int msiof3_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 2), -}; -static const unsigned int msiof3_clk_b_mux[] = { - MSIOF3_SCK_B_MARK, -}; -static const unsigned int msiof3_sync_b_pins[] = { - /* SYNC */ - RCAR_GP_PIN(1, 0), -}; -static const unsigned int msiof3_sync_b_mux[] = { - MSIOF3_SYNC_B_MARK, -}; -static const unsigned int msiof3_ss1_b_pins[] = { - /* SS1 */ - RCAR_GP_PIN(1, 4), -}; -static const unsigned int msiof3_ss1_b_mux[] = { - MSIOF3_SS1_B_MARK, -}; -static const unsigned int msiof3_ss2_b_pins[] = { - /* SS2 */ - RCAR_GP_PIN(1, 5), -}; -static const unsigned int msiof3_ss2_b_mux[] = { - MSIOF3_SS2_B_MARK, -}; -static const unsigned int msiof3_txd_b_pins[] = { - /* TXD */ - RCAR_GP_PIN(1, 1), -}; -static const unsigned int msiof3_txd_b_mux[] = { - MSIOF3_TXD_B_MARK, -}; -static const unsigned int msiof3_rxd_b_pins[] = { - /* RXD */ - RCAR_GP_PIN(1, 3), -}; -static const unsigned int msiof3_rxd_b_mux[] = { - MSIOF3_RXD_B_MARK, -}; -static const unsigned int msiof3_clk_c_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 12), -}; -static const unsigned int msiof3_clk_c_mux[] = { - MSIOF3_SCK_C_MARK, -}; -static const unsigned int msiof3_sync_c_pins[] = { - /* SYNC */ - RCAR_GP_PIN(1, 13), -}; -static const unsigned int msiof3_sync_c_mux[] = { - MSIOF3_SYNC_C_MARK, -}; -static const unsigned int msiof3_txd_c_pins[] = { - /* TXD */ - RCAR_GP_PIN(1, 15), -}; -static const unsigned int msiof3_txd_c_mux[] = { - MSIOF3_TXD_C_MARK, -}; -static const unsigned int msiof3_rxd_c_pins[] = { - /* RXD */ - RCAR_GP_PIN(1, 14), -}; -static const unsigned int msiof3_rxd_c_mux[] = { - MSIOF3_RXD_C_MARK, -}; -static const unsigned int msiof3_clk_d_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 22), -}; -static const unsigned int msiof3_clk_d_mux[] = { - MSIOF3_SCK_D_MARK, -}; -static const unsigned int msiof3_sync_d_pins[] = { - /* SYNC */ - RCAR_GP_PIN(1, 23), -}; -static const unsigned int msiof3_sync_d_mux[] = { - MSIOF3_SYNC_D_MARK, -}; -static const unsigned int msiof3_ss1_d_pins[] = { - /* SS1 */ - RCAR_GP_PIN(1, 26), -}; -static const unsigned int msiof3_ss1_d_mux[] = { - MSIOF3_SS1_D_MARK, -}; -static const unsigned int msiof3_txd_d_pins[] = { - /* TXD */ - RCAR_GP_PIN(1, 25), -}; -static const unsigned int msiof3_txd_d_mux[] = { - MSIOF3_TXD_D_MARK, -}; -static const unsigned int msiof3_rxd_d_pins[] = { - /* RXD */ - RCAR_GP_PIN(1, 24), -}; -static const unsigned int msiof3_rxd_d_mux[] = { - MSIOF3_RXD_D_MARK, -}; - -/* - PWM0 --------------------------------------------------------------------*/ -static const unsigned int pwm0_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 6), -}; -static const unsigned int pwm0_mux[] = { - PWM0_MARK, -}; -/* - PWM1 --------------------------------------------------------------------*/ -static const unsigned int pwm1_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 7), -}; -static const unsigned int pwm1_a_mux[] = { - PWM1_A_MARK, -}; -static const unsigned int pwm1_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 8), -}; -static const unsigned int pwm1_b_mux[] = { - PWM1_B_MARK, -}; -/* - PWM2 --------------------------------------------------------------------*/ -static const unsigned int pwm2_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 8), -}; -static const unsigned int pwm2_a_mux[] = { - PWM2_A_MARK, -}; -static const unsigned int pwm2_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 11), -}; -static const unsigned int pwm2_b_mux[] = { - PWM2_B_MARK, -}; -/* - PWM3 --------------------------------------------------------------------*/ -static const unsigned int pwm3_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 0), -}; -static const unsigned int pwm3_a_mux[] = { - PWM3_A_MARK, -}; -static const unsigned int pwm3_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 2), -}; -static const unsigned int pwm3_b_mux[] = { - PWM3_B_MARK, -}; -/* - PWM4 --------------------------------------------------------------------*/ -static const unsigned int pwm4_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 1), -}; -static const unsigned int pwm4_a_mux[] = { - PWM4_A_MARK, -}; -static const unsigned int pwm4_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 3), -}; -static const unsigned int pwm4_b_mux[] = { - PWM4_B_MARK, -}; -/* - PWM5 --------------------------------------------------------------------*/ -static const unsigned int pwm5_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 2), -}; -static const unsigned int pwm5_a_mux[] = { - PWM5_A_MARK, -}; -static const unsigned int pwm5_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 4), -}; -static const unsigned int pwm5_b_mux[] = { - PWM5_B_MARK, -}; -/* - PWM6 --------------------------------------------------------------------*/ -static const unsigned int pwm6_a_pins[] = { - /* PWM */ - RCAR_GP_PIN(1, 3), -}; -static const unsigned int pwm6_a_mux[] = { - PWM6_A_MARK, -}; -static const unsigned int pwm6_b_pins[] = { - /* PWM */ - RCAR_GP_PIN(2, 5), -}; -static const unsigned int pwm6_b_mux[] = { - PWM6_B_MARK, -}; - -/* - QSPI0 ------------------------------------------------------------------ */ -static const unsigned int qspi0_ctrl_pins[] = { - /* QSPI0_SPCLK, QSPI0_SSL */ - PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, -}; -static const unsigned int qspi0_ctrl_mux[] = { - QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, -}; -static const unsigned int qspi0_data_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3, -}; -static const unsigned int qspi0_data_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK, -}; -/* - QSPI1 ------------------------------------------------------------------ */ -static const unsigned int qspi1_ctrl_pins[] = { - /* QSPI1_SPCLK, QSPI1_SSL */ - PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, -}; -static const unsigned int qspi1_ctrl_mux[] = { - QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, -}; -static const unsigned int qspi1_data_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3, -}; -static const unsigned int qspi1_data_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK, -}; - -/* - SATA --------------------------------------------------------------------*/ -static const unsigned int sata0_devslp_a_pins[] = { - /* DEVSLP */ - RCAR_GP_PIN(6, 16), -}; -static const unsigned int sata0_devslp_a_mux[] = { - SATA_DEVSLP_A_MARK, -}; -static const unsigned int sata0_devslp_b_pins[] = { - /* DEVSLP */ - RCAR_GP_PIN(4, 6), -}; -static const unsigned int sata0_devslp_b_mux[] = { - SATA_DEVSLP_B_MARK, -}; - -/* - SCIF0 ------------------------------------------------------------------ */ -static const unsigned int scif0_data_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int scif0_data_mux[] = { - RX0_MARK, TX0_MARK, -}; -static const unsigned int scif0_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int scif0_clk_mux[] = { - SCK0_MARK, -}; -static const unsigned int scif0_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), -}; -static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_MARK, CTS0_N_MARK, -}; -/* - SCIF1 ------------------------------------------------------------------ */ -static const unsigned int scif1_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), -}; -static const unsigned int scif1_data_a_mux[] = { - RX1_A_MARK, TX1_A_MARK, -}; -static const unsigned int scif1_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int scif1_clk_mux[] = { - SCK1_MARK, -}; -static const unsigned int scif1_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), -}; -static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_MARK, CTS1_N_MARK, -}; - -static const unsigned int scif1_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), -}; -static const unsigned int scif1_data_b_mux[] = { - RX1_B_MARK, TX1_B_MARK, -}; -/* - SCIF2 ------------------------------------------------------------------ */ -static const unsigned int scif2_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), -}; -static const unsigned int scif2_data_a_mux[] = { - RX2_A_MARK, TX2_A_MARK, -}; -static const unsigned int scif2_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(5, 9), -}; -static const unsigned int scif2_clk_mux[] = { - SCK2_MARK, -}; -static const unsigned int scif2_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), -}; -static const unsigned int scif2_data_b_mux[] = { - RX2_B_MARK, TX2_B_MARK, -}; -/* - SCIF3 ------------------------------------------------------------------ */ -static const unsigned int scif3_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), -}; -static const unsigned int scif3_data_a_mux[] = { - RX3_A_MARK, TX3_A_MARK, -}; -static const unsigned int scif3_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 22), -}; -static const unsigned int scif3_clk_mux[] = { - SCK3_MARK, -}; -static const unsigned int scif3_ctrl_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), -}; -static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_MARK, CTS3_N_MARK, -}; -static const unsigned int scif3_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), -}; -static const unsigned int scif3_data_b_mux[] = { - RX3_B_MARK, TX3_B_MARK, -}; -/* - SCIF4 ------------------------------------------------------------------ */ -static const unsigned int scif4_data_a_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), -}; -static const unsigned int scif4_data_a_mux[] = { - RX4_A_MARK, TX4_A_MARK, -}; -static const unsigned int scif4_clk_a_pins[] = { - /* SCK */ - RCAR_GP_PIN(2, 10), -}; -static const unsigned int scif4_clk_a_mux[] = { - SCK4_A_MARK, -}; -static const unsigned int scif4_ctrl_a_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), -}; -static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_A_MARK, CTS4_N_A_MARK, -}; -static const unsigned int scif4_data_b_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; -static const unsigned int scif4_data_b_mux[] = { - RX4_B_MARK, TX4_B_MARK, -}; -static const unsigned int scif4_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 5), -}; -static const unsigned int scif4_clk_b_mux[] = { - SCK4_B_MARK, -}; -static const unsigned int scif4_ctrl_b_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), -}; -static const unsigned int scif4_ctrl_b_mux[] = { - RTS4_N_B_MARK, CTS4_N_B_MARK, -}; -static const unsigned int scif4_data_c_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), -}; -static const unsigned int scif4_data_c_mux[] = { - RX4_C_MARK, TX4_C_MARK, -}; -static const unsigned int scif4_clk_c_pins[] = { - /* SCK */ - RCAR_GP_PIN(0, 8), -}; -static const unsigned int scif4_clk_c_mux[] = { - SCK4_C_MARK, -}; -static const unsigned int scif4_ctrl_c_pins[] = { - /* RTS, CTS */ - RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), -}; -static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_C_MARK, CTS4_N_C_MARK, -}; -/* - SCIF5 ------------------------------------------------------------------ */ -static const unsigned int scif5_data_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), -}; -static const unsigned int scif5_data_mux[] = { - RX5_MARK, TX5_MARK, -}; -static const unsigned int scif5_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int scif5_clk_mux[] = { - SCK5_MARK, -}; - -/* - SCIF Clock ------------------------------------------------------------- */ -static const unsigned int scif_clk_a_pins[] = { - /* SCIF_CLK */ - RCAR_GP_PIN(6, 23), -}; -static const unsigned int scif_clk_a_mux[] = { - SCIF_CLK_A_MARK, -}; -static const unsigned int scif_clk_b_pins[] = { - /* SCIF_CLK */ - RCAR_GP_PIN(5, 9), -}; -static const unsigned int scif_clk_b_mux[] = { - SCIF_CLK_B_MARK, -}; - -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int sdhi0_data_mux[] = { - SD0_DAT0_MARK, SD0_DAT1_MARK, - SD0_DAT2_MARK, SD0_DAT3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SD0_CLK_MARK, SD0_CMD_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(3, 12), -}; -static const unsigned int sdhi0_cd_mux[] = { - SD0_CD_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(3, 13), -}; -static const unsigned int sdhi0_wp_mux[] = { - SD0_WP_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), -}; -static const unsigned int sdhi1_data_mux[] = { - SD1_DAT0_MARK, SD1_DAT1_MARK, - SD1_DAT2_MARK, SD1_DAT3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SD1_CLK_MARK, SD1_CMD_MARK, -}; -static const unsigned int sdhi1_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(3, 14), -}; -static const unsigned int sdhi1_cd_mux[] = { - SD1_CD_MARK, -}; -static const unsigned int sdhi1_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(3, 15), -}; -static const unsigned int sdhi1_wp_mux[] = { - SD1_WP_MARK, -}; -/* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data_pins[] = { - /* D[0:7] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), -}; -static const unsigned int sdhi2_data_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, - SD2_DAT4_MARK, SD2_DAT5_MARK, - SD2_DAT6_MARK, SD2_DAT7_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SD2_CLK_MARK, SD2_CMD_MARK, -}; -static const unsigned int sdhi2_cd_a_pins[] = { - /* CD */ - RCAR_GP_PIN(4, 13), -}; -static const unsigned int sdhi2_cd_a_mux[] = { - SD2_CD_A_MARK, -}; -static const unsigned int sdhi2_cd_b_pins[] = { - /* CD */ - RCAR_GP_PIN(5, 10), -}; -static const unsigned int sdhi2_cd_b_mux[] = { - SD2_CD_B_MARK, -}; -static const unsigned int sdhi2_wp_a_pins[] = { - /* WP */ - RCAR_GP_PIN(4, 14), -}; -static const unsigned int sdhi2_wp_a_mux[] = { - SD2_WP_A_MARK, -}; -static const unsigned int sdhi2_wp_b_pins[] = { - /* WP */ - RCAR_GP_PIN(5, 11), -}; -static const unsigned int sdhi2_wp_b_mux[] = { - SD2_WP_B_MARK, -}; -static const unsigned int sdhi2_ds_pins[] = { - /* DS */ - RCAR_GP_PIN(4, 6), -}; -static const unsigned int sdhi2_ds_mux[] = { - SD2_DS_MARK, -}; -/* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data_pins[] = { - /* D[0:7] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), - RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), - RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), -}; -static const unsigned int sdhi3_data_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, - SD3_DAT4_MARK, SD3_DAT5_MARK, - SD3_DAT6_MARK, SD3_DAT7_MARK, -}; -static const unsigned int sdhi3_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), -}; -static const unsigned int sdhi3_ctrl_mux[] = { - SD3_CLK_MARK, SD3_CMD_MARK, -}; -static const unsigned int sdhi3_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(4, 15), -}; -static const unsigned int sdhi3_cd_mux[] = { - SD3_CD_MARK, -}; -static const unsigned int sdhi3_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(4, 16), -}; -static const unsigned int sdhi3_wp_mux[] = { - SD3_WP_MARK, -}; -static const unsigned int sdhi3_ds_pins[] = { - /* DS */ - RCAR_GP_PIN(4, 17), -}; -static const unsigned int sdhi3_ds_mux[] = { - SD3_DS_MARK, -}; - -/* - SSI -------------------------------------------------------------------- */ -static const unsigned int ssi0_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int ssi0_data_mux[] = { - SSI_SDATA0_MARK, -}; -static const unsigned int ssi01239_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), -}; -static const unsigned int ssi01239_ctrl_mux[] = { - SSI_SCK01239_MARK, SSI_WS01239_MARK, -}; -static const unsigned int ssi1_data_a_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 3), -}; -static const unsigned int ssi1_data_a_mux[] = { - SSI_SDATA1_A_MARK, -}; -static const unsigned int ssi1_data_b_pins[] = { - /* SDATA */ - RCAR_GP_PIN(5, 12), -}; -static const unsigned int ssi1_data_b_mux[] = { - SSI_SDATA1_B_MARK, -}; -static const unsigned int ssi1_ctrl_a_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), -}; -static const unsigned int ssi1_ctrl_a_mux[] = { - SSI_SCK1_A_MARK, SSI_WS1_A_MARK, -}; -static const unsigned int ssi1_ctrl_b_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), -}; -static const unsigned int ssi1_ctrl_b_mux[] = { - SSI_SCK1_B_MARK, SSI_WS1_B_MARK, -}; -static const unsigned int ssi2_data_a_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 4), -}; -static const unsigned int ssi2_data_a_mux[] = { - SSI_SDATA2_A_MARK, -}; -static const unsigned int ssi2_data_b_pins[] = { - /* SDATA */ - RCAR_GP_PIN(5, 13), -}; -static const unsigned int ssi2_data_b_mux[] = { - SSI_SDATA2_B_MARK, -}; -static const unsigned int ssi2_ctrl_a_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), -}; -static const unsigned int ssi2_ctrl_a_mux[] = { - SSI_SCK2_A_MARK, SSI_WS2_A_MARK, -}; -static const unsigned int ssi2_ctrl_b_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), -}; -static const unsigned int ssi2_ctrl_b_mux[] = { - SSI_SCK2_B_MARK, SSI_WS2_B_MARK, -}; -static const unsigned int ssi3_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 7), -}; -static const unsigned int ssi3_data_mux[] = { - SSI_SDATA3_MARK, -}; -static const unsigned int ssi349_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), -}; -static const unsigned int ssi349_ctrl_mux[] = { - SSI_SCK349_MARK, SSI_WS349_MARK, -}; -static const unsigned int ssi4_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int ssi4_data_mux[] = { - SSI_SDATA4_MARK, -}; -static const unsigned int ssi4_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), -}; -static const unsigned int ssi4_ctrl_mux[] = { - SSI_SCK4_MARK, SSI_WS4_MARK, -}; -static const unsigned int ssi5_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 13), -}; -static const unsigned int ssi5_data_mux[] = { - SSI_SDATA5_MARK, -}; -static const unsigned int ssi5_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), -}; -static const unsigned int ssi5_ctrl_mux[] = { - SSI_SCK5_MARK, SSI_WS5_MARK, -}; -static const unsigned int ssi6_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 16), -}; -static const unsigned int ssi6_data_mux[] = { - SSI_SDATA6_MARK, -}; -static const unsigned int ssi6_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), -}; -static const unsigned int ssi6_ctrl_mux[] = { - SSI_SCK6_MARK, SSI_WS6_MARK, -}; -static const unsigned int ssi7_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 19), -}; -static const unsigned int ssi7_data_mux[] = { - SSI_SDATA7_MARK, -}; -static const unsigned int ssi78_ctrl_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), -}; -static const unsigned int ssi78_ctrl_mux[] = { - SSI_SCK78_MARK, SSI_WS78_MARK, -}; -static const unsigned int ssi8_data_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 20), -}; -static const unsigned int ssi8_data_mux[] = { - SSI_SDATA8_MARK, -}; -static const unsigned int ssi9_data_a_pins[] = { - /* SDATA */ - RCAR_GP_PIN(6, 21), -}; -static const unsigned int ssi9_data_a_mux[] = { - SSI_SDATA9_A_MARK, -}; -static const unsigned int ssi9_data_b_pins[] = { - /* SDATA */ - RCAR_GP_PIN(5, 14), -}; -static const unsigned int ssi9_data_b_mux[] = { - SSI_SDATA9_B_MARK, -}; -static const unsigned int ssi9_ctrl_a_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), -}; -static const unsigned int ssi9_ctrl_a_mux[] = { - SSI_SCK9_A_MARK, SSI_WS9_A_MARK, -}; -static const unsigned int ssi9_ctrl_b_pins[] = { - /* SCK, WS */ - RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), -}; -static const unsigned int ssi9_ctrl_b_mux[] = { - SSI_SCK9_B_MARK, SSI_WS9_B_MARK, -}; - -/* - TMU -------------------------------------------------------------------- */ -static const unsigned int tmu_tclk1_a_pins[] = { - /* TCLK */ - RCAR_GP_PIN(6, 23), -}; -static const unsigned int tmu_tclk1_a_mux[] = { - TCLK1_A_MARK, -}; -static const unsigned int tmu_tclk1_b_pins[] = { - /* TCLK */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int tmu_tclk1_b_mux[] = { - TCLK1_B_MARK, -}; -static const unsigned int tmu_tclk2_a_pins[] = { - /* TCLK */ - RCAR_GP_PIN(6, 19), -}; -static const unsigned int tmu_tclk2_a_mux[] = { - TCLK2_A_MARK, -}; -static const unsigned int tmu_tclk2_b_pins[] = { - /* TCLK */ - RCAR_GP_PIN(6, 28), -}; -static const unsigned int tmu_tclk2_b_mux[] = { - TCLK2_B_MARK, -}; - -/* - TPU ------------------------------------------------------------------- */ -static const unsigned int tpu_to0_pins[] = { - /* TPU0TO0 */ - RCAR_GP_PIN(6, 28), -}; -static const unsigned int tpu_to0_mux[] = { - TPU0TO0_MARK, -}; -static const unsigned int tpu_to1_pins[] = { - /* TPU0TO1 */ - RCAR_GP_PIN(6, 29), -}; -static const unsigned int tpu_to1_mux[] = { - TPU0TO1_MARK, -}; -static const unsigned int tpu_to2_pins[] = { - /* TPU0TO2 */ - RCAR_GP_PIN(6, 30), -}; -static const unsigned int tpu_to2_mux[] = { - TPU0TO2_MARK, -}; -static const unsigned int tpu_to3_pins[] = { - /* TPU0TO3 */ - RCAR_GP_PIN(6, 31), -}; -static const unsigned int tpu_to3_mux[] = { - TPU0TO3_MARK, -}; - -/* - USB0 ------------------------------------------------------------------- */ -static const unsigned int usb0_pins[] = { - /* PWEN, OVC */ - RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), -}; -static const unsigned int usb0_mux[] = { - USB0_PWEN_MARK, USB0_OVC_MARK, -}; -/* - USB1 ------------------------------------------------------------------- */ -static const unsigned int usb1_pins[] = { - /* PWEN, OVC */ - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), -}; -static const unsigned int usb1_mux[] = { - USB1_PWEN_MARK, USB1_OVC_MARK, -}; -/* - USB2 ------------------------------------------------------------------- */ -static const unsigned int usb2_pins[] = { - /* PWEN, OVC */ - RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), -}; -static const unsigned int usb2_mux[] = { - USB2_PWEN_MARK, USB2_OVC_MARK, -}; - -/* - USB30 ------------------------------------------------------------------ */ -static const unsigned int usb30_pins[] = { - /* PWEN, OVC */ - RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), -}; -static const unsigned int usb30_mux[] = { - USB30_PWEN_MARK, USB30_OVC_MARK, -}; -/* - USB31 ------------------------------------------------------------------ */ -static const unsigned int usb31_pins[] = { - /* PWEN, OVC */ - RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), -}; -static const unsigned int usb31_mux[] = { - USB31_PWEN_MARK, USB31_OVC_MARK, -}; - -/* - VIN4 ------------------------------------------------------------------- */ -static const unsigned int vin4_data18_a_pins[] = { - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), -}; -static const unsigned int vin4_data18_a_mux[] = { - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, -}; -static const unsigned int vin4_data18_b_pins[] = { - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), -}; -static const unsigned int vin4_data18_b_mux[] = { - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, -}; -static const unsigned int vin4_data_a_pins[] = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), -}; -static const unsigned int vin4_data_a_mux[] = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, -}; -static const unsigned int vin4_data_b_pins[] = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), -}; -static const unsigned int vin4_data_b_mux[] = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, -}; -static const unsigned int vin4_sync_pins[] = { - /* HSYNC#, VSYNC# */ - RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), -}; -static const unsigned int vin4_sync_mux[] = { - VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, -}; -static const unsigned int vin4_field_pins[] = { - /* FIELD */ - RCAR_GP_PIN(1, 16), -}; -static const unsigned int vin4_field_mux[] = { - VI4_FIELD_MARK, -}; -static const unsigned int vin4_clkenb_pins[] = { - /* CLKENB */ - RCAR_GP_PIN(1, 19), -}; -static const unsigned int vin4_clkenb_mux[] = { - VI4_CLKENB_MARK, -}; -static const unsigned int vin4_clk_pins[] = { - /* CLK */ - RCAR_GP_PIN(1, 27), -}; -static const unsigned int vin4_clk_mux[] = { - VI4_CLK_MARK, -}; - -/* - VIN5 ------------------------------------------------------------------- */ -static const unsigned int vin5_data_pins[] = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; -static const unsigned int vin5_data_mux[] = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, -}; -static const unsigned int vin5_sync_pins[] = { - /* HSYNC#, VSYNC# */ - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), -}; -static const unsigned int vin5_sync_mux[] = { - VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, -}; -static const unsigned int vin5_field_pins[] = { - RCAR_GP_PIN(1, 11), -}; -static const unsigned int vin5_field_mux[] = { - /* FIELD */ - VI5_FIELD_MARK, -}; -static const unsigned int vin5_clkenb_pins[] = { - RCAR_GP_PIN(1, 20), -}; -static const unsigned int vin5_clkenb_mux[] = { - /* CLKENB */ - VI5_CLKENB_MARK, -}; -static const unsigned int vin5_clk_pins[] = { - RCAR_GP_PIN(1, 21), -}; -static const unsigned int vin5_clk_mux[] = { - /* CLK */ - VI5_CLK_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a_a), - SH_PFC_PIN_GROUP(audio_clk_a_b), - SH_PFC_PIN_GROUP(audio_clk_a_c), - SH_PFC_PIN_GROUP(audio_clk_b_a), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c_a), - SH_PFC_PIN_GROUP(audio_clk_c_b), - SH_PFC_PIN_GROUP(audio_clkout_a), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(audio_clkout1_a), - SH_PFC_PIN_GROUP(audio_clkout1_b), - SH_PFC_PIN_GROUP(audio_clkout2_a), - SH_PFC_PIN_GROUP(audio_clkout2_b), - SH_PFC_PIN_GROUP(audio_clkout3_a), - SH_PFC_PIN_GROUP(audio_clkout3_b), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_avtp_pps), - SH_PFC_PIN_GROUP(avb_avtp_match_a), - SH_PFC_PIN_GROUP(avb_avtp_capture_a), - SH_PFC_PIN_GROUP(avb_avtp_match_b), - SH_PFC_PIN_GROUP(avb_avtp_capture_b), - SH_PFC_PIN_GROUP(can0_data_a), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), - SH_PFC_PIN_GROUP(drif0_ctrl_a), - SH_PFC_PIN_GROUP(drif0_data0_a), - SH_PFC_PIN_GROUP(drif0_data1_a), - SH_PFC_PIN_GROUP(drif0_ctrl_b), - SH_PFC_PIN_GROUP(drif0_data0_b), - SH_PFC_PIN_GROUP(drif0_data1_b), - SH_PFC_PIN_GROUP(drif0_ctrl_c), - SH_PFC_PIN_GROUP(drif0_data0_c), - SH_PFC_PIN_GROUP(drif0_data1_c), - SH_PFC_PIN_GROUP(drif1_ctrl_a), - SH_PFC_PIN_GROUP(drif1_data0_a), - SH_PFC_PIN_GROUP(drif1_data1_a), - SH_PFC_PIN_GROUP(drif1_ctrl_b), - SH_PFC_PIN_GROUP(drif1_data0_b), - SH_PFC_PIN_GROUP(drif1_data1_b), - SH_PFC_PIN_GROUP(drif1_ctrl_c), - SH_PFC_PIN_GROUP(drif1_data0_c), - SH_PFC_PIN_GROUP(drif1_data1_c), - SH_PFC_PIN_GROUP(drif2_ctrl_a), - SH_PFC_PIN_GROUP(drif2_data0_a), - SH_PFC_PIN_GROUP(drif2_data1_a), - SH_PFC_PIN_GROUP(drif2_ctrl_b), - SH_PFC_PIN_GROUP(drif2_data0_b), - SH_PFC_PIN_GROUP(drif2_data1_b), - SH_PFC_PIN_GROUP(drif3_ctrl_a), - SH_PFC_PIN_GROUP(drif3_data0_a), - SH_PFC_PIN_GROUP(drif3_data1_a), - SH_PFC_PIN_GROUP(drif3_ctrl_b), - SH_PFC_PIN_GROUP(drif3_data0_b), - SH_PFC_PIN_GROUP(drif3_data1_b), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_a), - SH_PFC_PIN_GROUP(hscif1_clk_a), - SH_PFC_PIN_GROUP(hscif1_ctrl_a), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_a), - SH_PFC_PIN_GROUP(hscif2_clk_a), - SH_PFC_PIN_GROUP(hscif2_ctrl_a), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_clk_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif3_data_a), - SH_PFC_PIN_GROUP(hscif3_clk), - SH_PFC_PIN_GROUP(hscif3_ctrl), - SH_PFC_PIN_GROUP(hscif3_data_b), - SH_PFC_PIN_GROUP(hscif3_data_c), - SH_PFC_PIN_GROUP(hscif3_data_d), - SH_PFC_PIN_GROUP(hscif4_data_a), - SH_PFC_PIN_GROUP(hscif4_clk), - SH_PFC_PIN_GROUP(hscif4_ctrl), - SH_PFC_PIN_GROUP(hscif4_data_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1_a), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c2_a), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c5), - SH_PFC_PIN_GROUP(i2c6_a), - SH_PFC_PIN_GROUP(i2c6_b), - SH_PFC_PIN_GROUP(i2c6_c), - SH_PFC_PIN_GROUP(intc_ex_irq0), - SH_PFC_PIN_GROUP(intc_ex_irq1), - SH_PFC_PIN_GROUP(intc_ex_irq2), - SH_PFC_PIN_GROUP(intc_ex_irq3), - SH_PFC_PIN_GROUP(intc_ex_irq4), - SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_txd), - SH_PFC_PIN_GROUP(msiof0_rxd), - SH_PFC_PIN_GROUP(msiof1_clk_a), - SH_PFC_PIN_GROUP(msiof1_sync_a), - SH_PFC_PIN_GROUP(msiof1_ss1_a), - SH_PFC_PIN_GROUP(msiof1_ss2_a), - SH_PFC_PIN_GROUP(msiof1_txd_a), - SH_PFC_PIN_GROUP(msiof1_rxd_a), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_txd_b), - SH_PFC_PIN_GROUP(msiof1_rxd_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_ss1_c), - SH_PFC_PIN_GROUP(msiof1_ss2_c), - SH_PFC_PIN_GROUP(msiof1_txd_c), - SH_PFC_PIN_GROUP(msiof1_rxd_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_ss2_d), - SH_PFC_PIN_GROUP(msiof1_txd_d), - SH_PFC_PIN_GROUP(msiof1_rxd_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_ss1_e), - SH_PFC_PIN_GROUP(msiof1_ss2_e), - SH_PFC_PIN_GROUP(msiof1_txd_e), - SH_PFC_PIN_GROUP(msiof1_rxd_e), - SH_PFC_PIN_GROUP(msiof1_clk_f), - SH_PFC_PIN_GROUP(msiof1_sync_f), - SH_PFC_PIN_GROUP(msiof1_ss1_f), - SH_PFC_PIN_GROUP(msiof1_ss2_f), - SH_PFC_PIN_GROUP(msiof1_txd_f), - SH_PFC_PIN_GROUP(msiof1_rxd_f), - SH_PFC_PIN_GROUP(msiof1_clk_g), - SH_PFC_PIN_GROUP(msiof1_sync_g), - SH_PFC_PIN_GROUP(msiof1_ss1_g), - SH_PFC_PIN_GROUP(msiof1_ss2_g), - SH_PFC_PIN_GROUP(msiof1_txd_g), - SH_PFC_PIN_GROUP(msiof1_rxd_g), - SH_PFC_PIN_GROUP(msiof2_clk_a), - SH_PFC_PIN_GROUP(msiof2_sync_a), - SH_PFC_PIN_GROUP(msiof2_ss1_a), - SH_PFC_PIN_GROUP(msiof2_ss2_a), - SH_PFC_PIN_GROUP(msiof2_txd_a), - SH_PFC_PIN_GROUP(msiof2_rxd_a), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_txd_b), - SH_PFC_PIN_GROUP(msiof2_rxd_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_ss1_c), - SH_PFC_PIN_GROUP(msiof2_ss2_c), - SH_PFC_PIN_GROUP(msiof2_txd_c), - SH_PFC_PIN_GROUP(msiof2_rxd_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_txd_d), - SH_PFC_PIN_GROUP(msiof2_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_a), - SH_PFC_PIN_GROUP(msiof3_sync_a), - SH_PFC_PIN_GROUP(msiof3_ss1_a), - SH_PFC_PIN_GROUP(msiof3_ss2_a), - SH_PFC_PIN_GROUP(msiof3_txd_a), - SH_PFC_PIN_GROUP(msiof3_rxd_a), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_ss1_b), - SH_PFC_PIN_GROUP(msiof3_ss2_b), - SH_PFC_PIN_GROUP(msiof3_txd_b), - SH_PFC_PIN_GROUP(msiof3_rxd_b), - SH_PFC_PIN_GROUP(msiof3_clk_c), - SH_PFC_PIN_GROUP(msiof3_sync_c), - SH_PFC_PIN_GROUP(msiof3_txd_c), - SH_PFC_PIN_GROUP(msiof3_rxd_c), - SH_PFC_PIN_GROUP(msiof3_clk_d), - SH_PFC_PIN_GROUP(msiof3_sync_d), - SH_PFC_PIN_GROUP(msiof3_ss1_d), - SH_PFC_PIN_GROUP(msiof3_txd_d), - SH_PFC_PIN_GROUP(msiof3_rxd_d), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm1_a), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2_a), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3_a), - SH_PFC_PIN_GROUP(pwm3_b), - SH_PFC_PIN_GROUP(pwm4_a), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5_a), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6_a), - SH_PFC_PIN_GROUP(pwm6_b), - SH_PFC_PIN_GROUP(qspi0_ctrl), - BUS_DATA_PIN_GROUP(qspi0_data, 2), - BUS_DATA_PIN_GROUP(qspi0_data, 4), - SH_PFC_PIN_GROUP(qspi1_ctrl), - BUS_DATA_PIN_GROUP(qspi1_data, 2), - BUS_DATA_PIN_GROUP(qspi1_data, 4), - SH_PFC_PIN_GROUP(sata0_devslp_a), - SH_PFC_PIN_GROUP(sata0_devslp_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif1_data_a), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif2_data_a), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif3_data_a), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_ctrl), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif4_data_a), - SH_PFC_PIN_GROUP(scif4_clk_a), - SH_PFC_PIN_GROUP(scif4_ctrl_a), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_clk_b), - SH_PFC_PIN_GROUP(scif4_ctrl_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif4_clk_c), - SH_PFC_PIN_GROUP(scif4_ctrl_c), - SH_PFC_PIN_GROUP(scif5_data), - SH_PFC_PIN_GROUP(scif5_clk), - SH_PFC_PIN_GROUP(scif_clk_a), - SH_PFC_PIN_GROUP(scif_clk_b), - BUS_DATA_PIN_GROUP(sdhi0_data, 1), - BUS_DATA_PIN_GROUP(sdhi0_data, 4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - BUS_DATA_PIN_GROUP(sdhi1_data, 1), - BUS_DATA_PIN_GROUP(sdhi1_data, 4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - BUS_DATA_PIN_GROUP(sdhi2_data, 1), - BUS_DATA_PIN_GROUP(sdhi2_data, 4), - BUS_DATA_PIN_GROUP(sdhi2_data, 8), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd_a), - SH_PFC_PIN_GROUP(sdhi2_wp_a), - SH_PFC_PIN_GROUP(sdhi2_cd_b), - SH_PFC_PIN_GROUP(sdhi2_wp_b), - SH_PFC_PIN_GROUP(sdhi2_ds), - BUS_DATA_PIN_GROUP(sdhi3_data, 1), - BUS_DATA_PIN_GROUP(sdhi3_data, 4), - BUS_DATA_PIN_GROUP(sdhi3_data, 8), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(sdhi3_ds), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi01239_ctrl), - SH_PFC_PIN_GROUP(ssi1_data_a), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl_a), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data_a), - SH_PFC_PIN_GROUP(ssi2_data_b), - SH_PFC_PIN_GROUP(ssi2_ctrl_a), - SH_PFC_PIN_GROUP(ssi2_ctrl_b), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi349_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi9_data_a), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl_a), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(tmu_tclk1_a), - SH_PFC_PIN_GROUP(tmu_tclk1_b), - SH_PFC_PIN_GROUP(tmu_tclk2_a), - SH_PFC_PIN_GROUP(tmu_tclk2_b), - SH_PFC_PIN_GROUP(tpu_to0), - SH_PFC_PIN_GROUP(tpu_to1), - SH_PFC_PIN_GROUP(tpu_to2), - SH_PFC_PIN_GROUP(tpu_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - SH_PFC_PIN_GROUP(usb30), - SH_PFC_PIN_GROUP(usb31), - BUS_DATA_PIN_GROUP(vin4_data, 8, _a), - BUS_DATA_PIN_GROUP(vin4_data, 10, _a), - BUS_DATA_PIN_GROUP(vin4_data, 12, _a), - BUS_DATA_PIN_GROUP(vin4_data, 16, _a), - SH_PFC_PIN_GROUP(vin4_data18_a), - BUS_DATA_PIN_GROUP(vin4_data, 20, _a), - BUS_DATA_PIN_GROUP(vin4_data, 24, _a), - BUS_DATA_PIN_GROUP(vin4_data, 8, _b), - BUS_DATA_PIN_GROUP(vin4_data, 10, _b), - BUS_DATA_PIN_GROUP(vin4_data, 12, _b), - BUS_DATA_PIN_GROUP(vin4_data, 16, _b), - SH_PFC_PIN_GROUP(vin4_data18_b), - BUS_DATA_PIN_GROUP(vin4_data, 20, _b), - BUS_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), - SH_PFC_PIN_GROUP(vin4_sync), - SH_PFC_PIN_GROUP(vin4_field), - SH_PFC_PIN_GROUP(vin4_clkenb), - SH_PFC_PIN_GROUP(vin4_clk), - BUS_DATA_PIN_GROUP(vin5_data, 8), - BUS_DATA_PIN_GROUP(vin5_data, 10), - BUS_DATA_PIN_GROUP(vin5_data, 12), - BUS_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), - SH_PFC_PIN_GROUP(vin5_sync), - SH_PFC_PIN_GROUP(vin5_field), - SH_PFC_PIN_GROUP(vin5_clkenb), - SH_PFC_PIN_GROUP(vin5_clk), -}; - -static const char * const audio_clk_groups[] = { - "audio_clk_a_a", - "audio_clk_a_b", - "audio_clk_a_c", - "audio_clk_b_a", - "audio_clk_b_b", - "audio_clk_c_a", - "audio_clk_c_b", - "audio_clkout_a", - "audio_clkout_b", - "audio_clkout_c", - "audio_clkout_d", - "audio_clkout1_a", - "audio_clkout1_b", - "audio_clkout2_a", - "audio_clkout2_b", - "audio_clkout3_a", - "audio_clkout3_b", -}; - -static const char * const avb_groups[] = { - "avb_link", - "avb_magic", - "avb_phy_int", - "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ - "avb_mdio", - "avb_mii", - "avb_avtp_pps", - "avb_avtp_match_a", - "avb_avtp_capture_a", - "avb_avtp_match_b", - "avb_avtp_capture_b", -}; - -static const char * const can0_groups[] = { - "can0_data_a", - "can0_data_b", -}; - -static const char * const can1_groups[] = { - "can1_data", -}; - -static const char * const can_clk_groups[] = { - "can_clk", -}; - -static const char * const canfd0_groups[] = { - "canfd0_data_a", - "canfd0_data_b", -}; - -static const char * const canfd1_groups[] = { - "canfd1_data", -}; - -static const char * const drif0_groups[] = { - "drif0_ctrl_a", - "drif0_data0_a", - "drif0_data1_a", - "drif0_ctrl_b", - "drif0_data0_b", - "drif0_data1_b", - "drif0_ctrl_c", - "drif0_data0_c", - "drif0_data1_c", -}; - -static const char * const drif1_groups[] = { - "drif1_ctrl_a", - "drif1_data0_a", - "drif1_data1_a", - "drif1_ctrl_b", - "drif1_data0_b", - "drif1_data1_b", - "drif1_ctrl_c", - "drif1_data0_c", - "drif1_data1_c", -}; - -static const char * const drif2_groups[] = { - "drif2_ctrl_a", - "drif2_data0_a", - "drif2_data1_a", - "drif2_ctrl_b", - "drif2_data0_b", - "drif2_data1_b", -}; - -static const char * const drif3_groups[] = { - "drif3_ctrl_a", - "drif3_data0_a", - "drif3_data1_a", - "drif3_ctrl_b", - "drif3_data0_b", - "drif3_data1_b", -}; - -static const char * const du_groups[] = { - "du_rgb666", - "du_rgb888", - "du_clk_out_0", - "du_clk_out_1", - "du_sync", - "du_oddf", - "du_cde", - "du_disp", -}; - -static const char * const hscif0_groups[] = { - "hscif0_data", - "hscif0_clk", - "hscif0_ctrl", -}; - -static const char * const hscif1_groups[] = { - "hscif1_data_a", - "hscif1_clk_a", - "hscif1_ctrl_a", - "hscif1_data_b", - "hscif1_clk_b", - "hscif1_ctrl_b", -}; - -static const char * const hscif2_groups[] = { - "hscif2_data_a", - "hscif2_clk_a", - "hscif2_ctrl_a", - "hscif2_data_b", - "hscif2_clk_b", - "hscif2_ctrl_b", -}; - -static const char * const hscif3_groups[] = { - "hscif3_data_a", - "hscif3_clk", - "hscif3_ctrl", - "hscif3_data_b", - "hscif3_data_c", - "hscif3_data_d", -}; - -static const char * const hscif4_groups[] = { - "hscif4_data_a", - "hscif4_clk", - "hscif4_ctrl", - "hscif4_data_b", -}; - -static const char * const i2c0_groups[] = { - "i2c0", -}; - -static const char * const i2c1_groups[] = { - "i2c1_a", - "i2c1_b", -}; - -static const char * const i2c2_groups[] = { - "i2c2_a", - "i2c2_b", -}; - -static const char * const i2c3_groups[] = { - "i2c3", -}; - -static const char * const i2c5_groups[] = { - "i2c5", -}; - -static const char * const i2c6_groups[] = { - "i2c6_a", - "i2c6_b", - "i2c6_c", -}; - -static const char * const intc_ex_groups[] = { - "intc_ex_irq0", - "intc_ex_irq1", - "intc_ex_irq2", - "intc_ex_irq3", - "intc_ex_irq4", - "intc_ex_irq5", -}; - -static const char * const mlb_3pin_groups[] = { - "mlb_3pin", -}; - -static const char * const msiof0_groups[] = { - "msiof0_clk", - "msiof0_sync", - "msiof0_ss1", - "msiof0_ss2", - "msiof0_txd", - "msiof0_rxd", -}; - -static const char * const msiof1_groups[] = { - "msiof1_clk_a", - "msiof1_sync_a", - "msiof1_ss1_a", - "msiof1_ss2_a", - "msiof1_txd_a", - "msiof1_rxd_a", - "msiof1_clk_b", - "msiof1_sync_b", - "msiof1_ss1_b", - "msiof1_ss2_b", - "msiof1_txd_b", - "msiof1_rxd_b", - "msiof1_clk_c", - "msiof1_sync_c", - "msiof1_ss1_c", - "msiof1_ss2_c", - "msiof1_txd_c", - "msiof1_rxd_c", - "msiof1_clk_d", - "msiof1_sync_d", - "msiof1_ss1_d", - "msiof1_ss2_d", - "msiof1_txd_d", - "msiof1_rxd_d", - "msiof1_clk_e", - "msiof1_sync_e", - "msiof1_ss1_e", - "msiof1_ss2_e", - "msiof1_txd_e", - "msiof1_rxd_e", - "msiof1_clk_f", - "msiof1_sync_f", - "msiof1_ss1_f", - "msiof1_ss2_f", - "msiof1_txd_f", - "msiof1_rxd_f", - "msiof1_clk_g", - "msiof1_sync_g", - "msiof1_ss1_g", - "msiof1_ss2_g", - "msiof1_txd_g", - "msiof1_rxd_g", -}; - -static const char * const msiof2_groups[] = { - "msiof2_clk_a", - "msiof2_sync_a", - "msiof2_ss1_a", - "msiof2_ss2_a", - "msiof2_txd_a", - "msiof2_rxd_a", - "msiof2_clk_b", - "msiof2_sync_b", - "msiof2_ss1_b", - "msiof2_ss2_b", - "msiof2_txd_b", - "msiof2_rxd_b", - "msiof2_clk_c", - "msiof2_sync_c", - "msiof2_ss1_c", - "msiof2_ss2_c", - "msiof2_txd_c", - "msiof2_rxd_c", - "msiof2_clk_d", - "msiof2_sync_d", - "msiof2_ss1_d", - "msiof2_ss2_d", - "msiof2_txd_d", - "msiof2_rxd_d", -}; - -static const char * const msiof3_groups[] = { - "msiof3_clk_a", - "msiof3_sync_a", - "msiof3_ss1_a", - "msiof3_ss2_a", - "msiof3_txd_a", - "msiof3_rxd_a", - "msiof3_clk_b", - "msiof3_sync_b", - "msiof3_ss1_b", - "msiof3_ss2_b", - "msiof3_txd_b", - "msiof3_rxd_b", - "msiof3_clk_c", - "msiof3_sync_c", - "msiof3_txd_c", - "msiof3_rxd_c", - "msiof3_clk_d", - "msiof3_sync_d", - "msiof3_ss1_d", - "msiof3_txd_d", - "msiof3_rxd_d", -}; - -static const char * const pwm0_groups[] = { - "pwm0", -}; - -static const char * const pwm1_groups[] = { - "pwm1_a", - "pwm1_b", -}; - -static const char * const pwm2_groups[] = { - "pwm2_a", - "pwm2_b", -}; - -static const char * const pwm3_groups[] = { - "pwm3_a", - "pwm3_b", -}; - -static const char * const pwm4_groups[] = { - "pwm4_a", - "pwm4_b", -}; - -static const char * const pwm5_groups[] = { - "pwm5_a", - "pwm5_b", -}; - -static const char * const pwm6_groups[] = { - "pwm6_a", - "pwm6_b", -}; - -static const char * const qspi0_groups[] = { - "qspi0_ctrl", - "qspi0_data2", - "qspi0_data4", -}; - -static const char * const qspi1_groups[] = { - "qspi1_ctrl", - "qspi1_data2", - "qspi1_data4", -}; - -static const char * const sata0_groups[] = { - "sata0_devslp_a", - "sata0_devslp_b", -}; - -static const char * const scif0_groups[] = { - "scif0_data", - "scif0_clk", - "scif0_ctrl", -}; - -static const char * const scif1_groups[] = { - "scif1_data_a", - "scif1_clk", - "scif1_ctrl", - "scif1_data_b", -}; - -static const char * const scif2_groups[] = { - "scif2_data_a", - "scif2_clk", - "scif2_data_b", -}; - -static const char * const scif3_groups[] = { - "scif3_data_a", - "scif3_clk", - "scif3_ctrl", - "scif3_data_b", -}; - -static const char * const scif4_groups[] = { - "scif4_data_a", - "scif4_clk_a", - "scif4_ctrl_a", - "scif4_data_b", - "scif4_clk_b", - "scif4_ctrl_b", - "scif4_data_c", - "scif4_clk_c", - "scif4_ctrl_c", -}; - -static const char * const scif5_groups[] = { - "scif5_data", - "scif5_clk", -}; - -static const char * const scif_clk_groups[] = { - "scif_clk_a", - "scif_clk_b", -}; - -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; - -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", - "sdhi1_cd", - "sdhi1_wp", -}; - -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_data8", - "sdhi2_ctrl", - "sdhi2_cd_a", - "sdhi2_wp_a", - "sdhi2_cd_b", - "sdhi2_wp_b", - "sdhi2_ds", -}; - -static const char * const sdhi3_groups[] = { - "sdhi3_data1", - "sdhi3_data4", - "sdhi3_data8", - "sdhi3_ctrl", - "sdhi3_cd", - "sdhi3_wp", - "sdhi3_ds", -}; - -static const char * const ssi_groups[] = { - "ssi0_data", - "ssi01239_ctrl", - "ssi1_data_a", - "ssi1_data_b", - "ssi1_ctrl_a", - "ssi1_ctrl_b", - "ssi2_data_a", - "ssi2_data_b", - "ssi2_ctrl_a", - "ssi2_ctrl_b", - "ssi3_data", - "ssi349_ctrl", - "ssi4_data", - "ssi4_ctrl", - "ssi5_data", - "ssi5_ctrl", - "ssi6_data", - "ssi6_ctrl", - "ssi7_data", - "ssi78_ctrl", - "ssi8_data", - "ssi9_data_a", - "ssi9_data_b", - "ssi9_ctrl_a", - "ssi9_ctrl_b", -}; - -static const char * const tmu_groups[] = { - "tmu_tclk1_a", - "tmu_tclk1_b", - "tmu_tclk2_a", - "tmu_tclk2_b", -}; - -static const char * const tpu_groups[] = { - "tpu_to0", - "tpu_to1", - "tpu_to2", - "tpu_to3", -}; - -static const char * const usb0_groups[] = { - "usb0", -}; - -static const char * const usb1_groups[] = { - "usb1", -}; - -static const char * const usb2_groups[] = { - "usb2", -}; - -static const char * const usb30_groups[] = { - "usb30", -}; - -static const char * const usb31_groups[] = { - "usb31", -}; - -static const char * const vin4_groups[] = { - "vin4_data8_a", - "vin4_data10_a", - "vin4_data12_a", - "vin4_data16_a", - "vin4_data18_a", - "vin4_data20_a", - "vin4_data24_a", - "vin4_data8_b", - "vin4_data10_b", - "vin4_data12_b", - "vin4_data16_b", - "vin4_data18_b", - "vin4_data20_b", - "vin4_data24_b", - "vin4_g8", - "vin4_sync", - "vin4_field", - "vin4_clkenb", - "vin4_clk", -}; - -static const char * const vin5_groups[] = { - "vin5_data8", - "vin5_data10", - "vin5_data12", - "vin5_data16", - "vin5_high8", - "vin5_sync", - "vin5_field", - "vin5_clkenb", - "vin5_clk", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(can_clk), - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), - SH_PFC_FUNCTION(drif0), - SH_PFC_FUNCTION(drif1), - SH_PFC_FUNCTION(drif2), - SH_PFC_FUNCTION(drif3), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(hscif3), - SH_PFC_FUNCTION(hscif4), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c5), - SH_PFC_FUNCTION(i2c6), - SH_PFC_FUNCTION(intc_ex), - SH_PFC_FUNCTION(mlb_3pin), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi0), - SH_PFC_FUNCTION(qspi1), - SH_PFC_FUNCTION(sata0), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tmu), - SH_PFC_FUNCTION(tpu), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(usb30), - SH_PFC_FUNCTION(usb31), - SH_PFC_FUNCTION(vin4), - SH_PFC_FUNCTION(vin5), -}; - -static const struct pinmux_cfg_reg pinmux_config_regs[] = { -#define F_(x, y) FN_##y -#define FM(x) FN_##x - { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, - GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1), - GROUP( - /* GP0_31_16 RESERVED */ - GP_0_15_FN, GPSR0_15, - GP_0_14_FN, GPSR0_14, - GP_0_13_FN, GPSR0_13, - GP_0_12_FN, GPSR0_12, - GP_0_11_FN, GPSR0_11, - GP_0_10_FN, GPSR0_10, - GP_0_9_FN, GPSR0_9, - GP_0_8_FN, GPSR0_8, - GP_0_7_FN, GPSR0_7, - GP_0_6_FN, GPSR0_6, - GP_0_5_FN, GPSR0_5, - GP_0_4_FN, GPSR0_4, - GP_0_3_FN, GPSR0_3, - GP_0_2_FN, GPSR0_2, - GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, )) - }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_1_27_FN, GPSR1_27, - GP_1_26_FN, GPSR1_26, - GP_1_25_FN, GPSR1_25, - GP_1_24_FN, GPSR1_24, - GP_1_23_FN, GPSR1_23, - GP_1_22_FN, GPSR1_22, - GP_1_21_FN, GPSR1_21, - GP_1_20_FN, GPSR1_20, - GP_1_19_FN, GPSR1_19, - GP_1_18_FN, GPSR1_18, - GP_1_17_FN, GPSR1_17, - GP_1_16_FN, GPSR1_16, - GP_1_15_FN, GPSR1_15, - GP_1_14_FN, GPSR1_14, - GP_1_13_FN, GPSR1_13, - GP_1_12_FN, GPSR1_12, - GP_1_11_FN, GPSR1_11, - GP_1_10_FN, GPSR1_10, - GP_1_9_FN, GPSR1_9, - GP_1_8_FN, GPSR1_8, - GP_1_7_FN, GPSR1_7, - GP_1_6_FN, GPSR1_6, - GP_1_5_FN, GPSR1_5, - GP_1_4_FN, GPSR1_4, - GP_1_3_FN, GPSR1_3, - GP_1_2_FN, GPSR1_2, - GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, )) - }, - { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, - GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1), - GROUP( - /* GP2_31_15 RESERVED */ - GP_2_14_FN, GPSR2_14, - GP_2_13_FN, GPSR2_13, - GP_2_12_FN, GPSR2_12, - GP_2_11_FN, GPSR2_11, - GP_2_10_FN, GPSR2_10, - GP_2_9_FN, GPSR2_9, - GP_2_8_FN, GPSR2_8, - GP_2_7_FN, GPSR2_7, - GP_2_6_FN, GPSR2_6, - GP_2_5_FN, GPSR2_5, - GP_2_4_FN, GPSR2_4, - GP_2_3_FN, GPSR2_3, - GP_2_2_FN, GPSR2_2, - GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, )) - }, - { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, - GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1), - GROUP( - /* GP3_31_16 RESERVED */ - GP_3_15_FN, GPSR3_15, - GP_3_14_FN, GPSR3_14, - GP_3_13_FN, GPSR3_13, - GP_3_12_FN, GPSR3_12, - GP_3_11_FN, GPSR3_11, - GP_3_10_FN, GPSR3_10, - GP_3_9_FN, GPSR3_9, - GP_3_8_FN, GPSR3_8, - GP_3_7_FN, GPSR3_7, - GP_3_6_FN, GPSR3_6, - GP_3_5_FN, GPSR3_5, - GP_3_4_FN, GPSR3_4, - GP_3_3_FN, GPSR3_3, - GP_3_2_FN, GPSR3_2, - GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, )) - }, - { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, - GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1), - GROUP( - /* GP4_31_18 RESERVED */ - GP_4_17_FN, GPSR4_17, - GP_4_16_FN, GPSR4_16, - GP_4_15_FN, GPSR4_15, - GP_4_14_FN, GPSR4_14, - GP_4_13_FN, GPSR4_13, - GP_4_12_FN, GPSR4_12, - GP_4_11_FN, GPSR4_11, - GP_4_10_FN, GPSR4_10, - GP_4_9_FN, GPSR4_9, - GP_4_8_FN, GPSR4_8, - GP_4_7_FN, GPSR4_7, - GP_4_6_FN, GPSR4_6, - GP_4_5_FN, GPSR4_5, - GP_4_4_FN, GPSR4_4, - GP_4_3_FN, GPSR4_3, - GP_4_2_FN, GPSR4_2, - GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, )) - }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GPSR5_25, - GP_5_24_FN, GPSR5_24, - GP_5_23_FN, GPSR5_23, - GP_5_22_FN, GPSR5_22, - GP_5_21_FN, GPSR5_21, - GP_5_20_FN, GPSR5_20, - GP_5_19_FN, GPSR5_19, - GP_5_18_FN, GPSR5_18, - GP_5_17_FN, GPSR5_17, - GP_5_16_FN, GPSR5_16, - GP_5_15_FN, GPSR5_15, - GP_5_14_FN, GPSR5_14, - GP_5_13_FN, GPSR5_13, - GP_5_12_FN, GPSR5_12, - GP_5_11_FN, GPSR5_11, - GP_5_10_FN, GPSR5_10, - GP_5_9_FN, GPSR5_9, - GP_5_8_FN, GPSR5_8, - GP_5_7_FN, GPSR5_7, - GP_5_6_FN, GPSR5_6, - GP_5_5_FN, GPSR5_5, - GP_5_4_FN, GPSR5_4, - GP_5_3_FN, GPSR5_3, - GP_5_2_FN, GPSR5_2, - GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, )) - }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( - GP_6_31_FN, GPSR6_31, - GP_6_30_FN, GPSR6_30, - GP_6_29_FN, GPSR6_29, - GP_6_28_FN, GPSR6_28, - GP_6_27_FN, GPSR6_27, - GP_6_26_FN, GPSR6_26, - GP_6_25_FN, GPSR6_25, - GP_6_24_FN, GPSR6_24, - GP_6_23_FN, GPSR6_23, - GP_6_22_FN, GPSR6_22, - GP_6_21_FN, GPSR6_21, - GP_6_20_FN, GPSR6_20, - GP_6_19_FN, GPSR6_19, - GP_6_18_FN, GPSR6_18, - GP_6_17_FN, GPSR6_17, - GP_6_16_FN, GPSR6_16, - GP_6_15_FN, GPSR6_15, - GP_6_14_FN, GPSR6_14, - GP_6_13_FN, GPSR6_13, - GP_6_12_FN, GPSR6_12, - GP_6_11_FN, GPSR6_11, - GP_6_10_FN, GPSR6_10, - GP_6_9_FN, GPSR6_9, - GP_6_8_FN, GPSR6_8, - GP_6_7_FN, GPSR6_7, - GP_6_6_FN, GPSR6_6, - GP_6_5_FN, GPSR6_5, - GP_6_4_FN, GPSR6_4, - GP_6_3_FN, GPSR6_3, - GP_6_2_FN, GPSR6_2, - GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, )) - }, - { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, - GROUP(-28, 1, 1, 1, 1), - GROUP( - /* GP7_31_4 RESERVED */ - GP_7_3_FN, GPSR7_3, - GP_7_2_FN, GPSR7_2, - GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, )) - }, -#undef F_ -#undef FM - -#define F_(x, y) x, -#define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( - IP0_31_28 - IP0_27_24 - IP0_23_20 - IP0_19_16 - IP0_15_12 - IP0_11_8 - IP0_7_4 - IP0_3_0 )) - }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( - IP1_31_28 - IP1_27_24 - IP1_23_20 - IP1_19_16 - IP1_15_12 - IP1_11_8 - IP1_7_4 - IP1_3_0 )) - }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( - IP2_31_28 - IP2_27_24 - IP2_23_20 - IP2_19_16 - IP2_15_12 - IP2_11_8 - IP2_7_4 - IP2_3_0 )) - }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( - IP3_31_28 - IP3_27_24 - IP3_23_20 - IP3_19_16 - IP3_15_12 - IP3_11_8 - IP3_7_4 - IP3_3_0 )) - }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( - IP4_31_28 - IP4_27_24 - IP4_23_20 - IP4_19_16 - IP4_15_12 - IP4_11_8 - IP4_7_4 - IP4_3_0 )) - }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( - IP5_31_28 - IP5_27_24 - IP5_23_20 - IP5_19_16 - IP5_15_12 - IP5_11_8 - IP5_7_4 - IP5_3_0 )) - }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( - IP6_31_28 - IP6_27_24 - IP6_23_20 - IP6_19_16 - IP6_15_12 - IP6_11_8 - IP6_7_4 - IP6_3_0 )) - }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( - IP7_31_28 - IP7_27_24 - IP7_23_20 - IP7_19_16 - IP7_15_12 - IP7_11_8 - IP7_7_4 - IP7_3_0 )) - }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( - IP8_31_28 - IP8_27_24 - IP8_23_20 - IP8_19_16 - IP8_15_12 - IP8_11_8 - IP8_7_4 - IP8_3_0 )) - }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( - IP9_31_28 - IP9_27_24 - IP9_23_20 - IP9_19_16 - IP9_15_12 - IP9_11_8 - IP9_7_4 - IP9_3_0 )) - }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( - IP10_31_28 - IP10_27_24 - IP10_23_20 - IP10_19_16 - IP10_15_12 - IP10_11_8 - IP10_7_4 - IP10_3_0 )) - }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( - IP11_31_28 - IP11_27_24 - IP11_23_20 - IP11_19_16 - IP11_15_12 - IP11_11_8 - IP11_7_4 - IP11_3_0 )) - }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( - IP12_31_28 - IP12_27_24 - IP12_23_20 - IP12_19_16 - IP12_15_12 - IP12_11_8 - IP12_7_4 - IP12_3_0 )) - }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( - IP13_31_28 - IP13_27_24 - IP13_23_20 - IP13_19_16 - IP13_15_12 - IP13_11_8 - IP13_7_4 - IP13_3_0 )) - }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( - IP14_31_28 - IP14_27_24 - IP14_23_20 - IP14_19_16 - IP14_15_12 - IP14_11_8 - IP14_7_4 - IP14_3_0 )) - }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( - IP15_31_28 - IP15_27_24 - IP15_23_20 - IP15_19_16 - IP15_15_12 - IP15_11_8 - IP15_7_4 - IP15_3_0 )) - }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( - IP16_31_28 - IP16_27_24 - IP16_23_20 - IP16_19_16 - IP16_15_12 - IP16_11_8 - IP16_7_4 - IP16_3_0 )) - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32, - GROUP(-24, 4, 4), - GROUP( - /* IP17_31_8 RESERVED */ - IP17_7_4 - IP17_3_0 )) - }, -#undef F_ -#undef FM - -#define F_(x, y) x, -#define FM(x) FN_##x, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(-1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1, - 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, -1), - GROUP( - /* RESERVED 31 */ - MOD_SEL0_30_29 - MOD_SEL0_28_27 - MOD_SEL0_26_25_24 - MOD_SEL0_23 - MOD_SEL0_22 - MOD_SEL0_21_20 - MOD_SEL0_19 - MOD_SEL0_18 - MOD_SEL0_17 - MOD_SEL0_16_15 - MOD_SEL0_14 - MOD_SEL0_13 - MOD_SEL0_12 - MOD_SEL0_11 - MOD_SEL0_10 - MOD_SEL0_9 - MOD_SEL0_8 - MOD_SEL0_7_6 - MOD_SEL0_5_4 - MOD_SEL0_3 - MOD_SEL0_2_1 - /* RESERVED 0 */ )) - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, - 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), - GROUP( - MOD_SEL1_31_30 - MOD_SEL1_29_28_27 - MOD_SEL1_26 - MOD_SEL1_25_24 - MOD_SEL1_23_22_21 - MOD_SEL1_20 - MOD_SEL1_19 - MOD_SEL1_18_17 - MOD_SEL1_16 - MOD_SEL1_15_14 - MOD_SEL1_13 - MOD_SEL1_12 - MOD_SEL1_11 - MOD_SEL1_10 - MOD_SEL1_9 - /* RESERVED 8, 7 */ - MOD_SEL1_6 - MOD_SEL1_5 - MOD_SEL1_4 - MOD_SEL1_3 - MOD_SEL1_2 - MOD_SEL1_1 - MOD_SEL1_0 )) - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - GROUP(1, 1, 1, -28, 1), - GROUP( - MOD_SEL2_31 - MOD_SEL2_30 - MOD_SEL2_29 - /* RESERVED 28-1 */ - MOD_SEL2_0 )) - }, - { }, -}; - -static const struct pinmux_drive_reg pinmux_drive_regs[] = { - { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ - { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ - { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ - { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ - { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ - { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ - { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ - { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ - { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ - { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ - { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ - { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ - { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ - { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ - { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ - { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ - { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ - { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ - { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ - { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ - { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ - { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { - { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ - { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ - { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ - { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { - { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ - { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ - { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ - { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ - { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ - { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ - { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { - { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ - { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ - { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ - { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ - { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ - { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ - { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ - { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { - { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ - { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ - { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ - { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ - { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ - { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ - { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ - { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { - { PIN_CLKOUT, 28, 3 }, /* CLKOUT */ - { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ - { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ - { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ - { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ - { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ - { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ - { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { - { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ - { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ - { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ - { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ - { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ - { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ - { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { - { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ - { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ - { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ - { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ - { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ - { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ - { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ - { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ - { PIN_TMS, 4, 2 }, /* TMS */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_TDO, 28, 2 }, /* TDO */ - { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { - { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ - { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { - { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { - { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ - { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { - { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ - { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ - { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ - { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ - { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ - { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ - { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ - { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ - { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ - { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ - { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ - { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { - { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ - { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ - { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ - { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ - { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { - { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ - { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ - { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { - { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ - { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { - { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { - { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ - { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ - { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ - { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ - } }, - { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { - { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ - { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */ - } }, - { }, -}; - -enum ioctrl_regs { - POCCTRL, - TDSELCTRL, -}; - -static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [POCCTRL] = { 0xe6060380, }, - [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, -}; - -static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) -{ - int bit = -EINVAL; - - *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; - - if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) - bit = pin & 0x1f; - - if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) - bit = (pin & 0x1f) + 12; - - return bit; -} - -static const struct pinmux_bias_reg pinmux_bias_regs[] = { - { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ - [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ - [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ - [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ - [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ - [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ - [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ - [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ - [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ - [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ - [12] = PIN_RPC_INT_N, /* RPC_INT# */ - [13] = PIN_RPC_WP_N, /* RPC_WP# */ - [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ - [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ - [16] = PIN_AVB_RXC, /* AVB_RXC */ - [17] = PIN_AVB_RD0, /* AVB_RD0 */ - [18] = PIN_AVB_RD1, /* AVB_RD1 */ - [19] = PIN_AVB_RD2, /* AVB_RD2 */ - [20] = PIN_AVB_RD3, /* AVB_RD3 */ - [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ - [22] = PIN_AVB_TXC, /* AVB_TXC */ - [23] = PIN_AVB_TD0, /* AVB_TD0 */ - [24] = PIN_AVB_TD1, /* AVB_TD1 */ - [25] = PIN_AVB_TD2, /* AVB_TD2 */ - [26] = PIN_AVB_TD3, /* AVB_TD3 */ - [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ - [28] = PIN_AVB_MDIO, /* AVB_MDIO */ - [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ - [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ - [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ - } }, - { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { - [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ - [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ - [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ - [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ - [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ - [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ - [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ - [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ - [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ - [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ - [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ - [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ - [12] = RCAR_GP_PIN(1, 0), /* A0 */ - [13] = RCAR_GP_PIN(1, 1), /* A1 */ - [14] = RCAR_GP_PIN(1, 2), /* A2 */ - [15] = RCAR_GP_PIN(1, 3), /* A3 */ - [16] = RCAR_GP_PIN(1, 4), /* A4 */ - [17] = RCAR_GP_PIN(1, 5), /* A5 */ - [18] = RCAR_GP_PIN(1, 6), /* A6 */ - [19] = RCAR_GP_PIN(1, 7), /* A7 */ - [20] = RCAR_GP_PIN(1, 8), /* A8 */ - [21] = RCAR_GP_PIN(1, 9), /* A9 */ - [22] = RCAR_GP_PIN(1, 10), /* A10 */ - [23] = RCAR_GP_PIN(1, 11), /* A11 */ - [24] = RCAR_GP_PIN(1, 12), /* A12 */ - [25] = RCAR_GP_PIN(1, 13), /* A13 */ - [26] = RCAR_GP_PIN(1, 14), /* A14 */ - [27] = RCAR_GP_PIN(1, 15), /* A15 */ - [28] = RCAR_GP_PIN(1, 16), /* A16 */ - [29] = RCAR_GP_PIN(1, 17), /* A17 */ - [30] = RCAR_GP_PIN(1, 18), /* A18 */ - [31] = RCAR_GP_PIN(1, 19), /* A19 */ - } }, - { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { - [ 0] = PIN_CLKOUT, /* CLKOUT */ - [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ - [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */ - [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ - [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ - [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ - [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ - [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ - [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ - [10] = RCAR_GP_PIN(0, 0), /* D0 */ - [11] = RCAR_GP_PIN(0, 1), /* D1 */ - [12] = RCAR_GP_PIN(0, 2), /* D2 */ - [13] = RCAR_GP_PIN(0, 3), /* D3 */ - [14] = RCAR_GP_PIN(0, 4), /* D4 */ - [15] = RCAR_GP_PIN(0, 5), /* D5 */ - [16] = RCAR_GP_PIN(0, 6), /* D6 */ - [17] = RCAR_GP_PIN(0, 7), /* D7 */ - [18] = RCAR_GP_PIN(0, 8), /* D8 */ - [19] = RCAR_GP_PIN(0, 9), /* D9 */ - [20] = RCAR_GP_PIN(0, 10), /* D10 */ - [21] = RCAR_GP_PIN(0, 11), /* D11 */ - [22] = RCAR_GP_PIN(0, 12), /* D12 */ - [23] = RCAR_GP_PIN(0, 13), /* D13 */ - [24] = RCAR_GP_PIN(0, 14), /* D14 */ - [25] = RCAR_GP_PIN(0, 15), /* D15 */ - [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ - [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ - [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ - [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ - } }, - { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ - [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ - [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ - [ 3] = PIN_EXTALR, /* EXTALR*/ - [ 4] = PIN_TRST_N, /* TRST# */ - [ 5] = PIN_TCK, /* TCK */ - [ 6] = PIN_TMS, /* TMS */ - [ 7] = PIN_TDI, /* TDI */ - [ 8] = SH_PFC_PIN_NONE, - [ 9] = PIN_ASEBRK, /* ASEBRK */ - [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ - [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ - [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ - [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ - [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ - [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ - [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ - [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ - [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ - [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ - [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ - [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ - [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ - [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ - [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ - [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ - [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ - [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ - [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ - [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ - [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ - } }, - { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { - [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ - [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ - [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ - [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ - [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ - [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ - [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ - [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ - [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ - [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ - [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ - [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ - [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ - [13] = RCAR_GP_PIN(5, 1), /* RX0 */ - [14] = RCAR_GP_PIN(5, 2), /* TX0 */ - [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ - [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ - [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ - [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ - [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ - [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ - [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ - [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ - [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ - [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ - [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ - [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ - [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ - [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ - [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ - [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ - [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ - } }, - { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { - [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ - [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ - [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ - [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ - [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ - [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_MLB_REF, /* MLB_REF */ - [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ - [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ - [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ - [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ - [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ - [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ - [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ - [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ - [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ - [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ - [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ - [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ - [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ - [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ - [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ - [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ - [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ - [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ - [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ - [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ - [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ - [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ - [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ - [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ - [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ - } }, - { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { - [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ - [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ - [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ - [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ - [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ - [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */ - [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */ - [ 7] = SH_PFC_PIN_NONE, - [ 8] = SH_PFC_PIN_NONE, - [ 9] = SH_PFC_PIN_NONE, - [10] = SH_PFC_PIN_NONE, - [11] = SH_PFC_PIN_NONE, - [12] = SH_PFC_PIN_NONE, - [13] = SH_PFC_PIN_NONE, - [14] = SH_PFC_PIN_NONE, - [15] = SH_PFC_PIN_NONE, - [16] = SH_PFC_PIN_NONE, - [17] = SH_PFC_PIN_NONE, - [18] = SH_PFC_PIN_NONE, - [19] = SH_PFC_PIN_NONE, - [20] = SH_PFC_PIN_NONE, - [21] = SH_PFC_PIN_NONE, - [22] = SH_PFC_PIN_NONE, - [23] = SH_PFC_PIN_NONE, - [24] = SH_PFC_PIN_NONE, - [25] = SH_PFC_PIN_NONE, - [26] = SH_PFC_PIN_NONE, - [27] = SH_PFC_PIN_NONE, - [28] = SH_PFC_PIN_NONE, - [29] = SH_PFC_PIN_NONE, - [30] = SH_PFC_PIN_NONE, - [31] = SH_PFC_PIN_NONE, - } }, - { /* sentinel */ }, -}; - -static const struct sh_pfc_soc_operations r8a77950_pfc_ops = { - .pin_to_pocctrl = r8a77950_pin_to_pocctrl, - .get_bias = rcar_pinmux_get_bias, - .set_bias = rcar_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info r8a77950_pinmux_info = { - .name = "r8a77950_pfc", - .ops = &r8a77950_pfc_ops, - .unlock_reg = 0xe6060000, /* PMMR */ - - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .cfg_regs = pinmux_config_regs, - .drive_regs = pinmux_drive_regs, - .bias_regs = pinmux_bias_regs, - .ioctrl_regs = pinmux_ioctrl_regs, - - .pinmux_data = pinmux_data, - .pinmux_data_size = ARRAY_SIZE(pinmux_data), -}; diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index d4d271dff055..a1d74f61fd8c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -17,12 +17,12 @@ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) @@ -5610,7 +5610,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 16-1 */ MOD_SEL2_0 )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -5861,7 +5861,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -5872,7 +5872,7 @@ enum ioctrl_regs { static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -6129,7 +6129,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a77951_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a0096ef5e68d..807834f319f0 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -22,12 +22,12 @@ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) @@ -5565,7 +5565,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 16-1 */ MOD_SEL2_0 )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -5813,7 +5813,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -5824,7 +5824,7 @@ enum ioctrl_regs { static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -6081,7 +6081,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a7796_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index acd0bdf13018..e7c88a5d983f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -23,12 +23,12 @@ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) @@ -5806,7 +5806,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 16-1 */ MOD_SEL2_0 )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -6054,7 +6054,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -6065,7 +6065,7 @@ enum ioctrl_regs { static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -6322,7 +6322,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 4a7803eaafaa..5b66d7b1af95 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -19,10 +19,10 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -34,7 +34,8 @@ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ - PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -2342,7 +2343,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_1 MOD_SEL0_0 )) }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -2357,26 +2358,37 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL1] = { 0xe6060384 }, [POCCTRL2] = { 0xe6060388 }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; - if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + switch (pin) { + case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit; - if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + + case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit + 22; - *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; - if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit - 10; - if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) + + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit + 7; - return -EINVAL; + case PIN_VDDQ_AVB0: + *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; + return 0; + + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index ac03309c5c0c..384faa0d6937 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -19,10 +19,10 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -35,7 +35,9 @@ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \ + PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -2813,7 +2815,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_1 MOD_SEL0_0 )) }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -2830,31 +2832,46 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL2] = { 0xe6060388, }, [POCCTRL3] = { 0xe606038c, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; - if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + switch (pin) { + case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit; - else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + + case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit + 22; - *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; - if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit - 10; - if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || - (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) + + case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24): + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit + 7; - *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; - if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) + case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29): + *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; return pin - 25; - return -EINVAL; + case PIN_VDDQ_AVB: + *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg; + return 0; + + case PIN_VDDQ_GE: + *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg; + return 1; + + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index b0936962fad7..262390dd7d67 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -22,12 +22,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -56,7 +56,8 @@ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ - PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP) + PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -507,7 +508,8 @@ MOD_SEL0_1_0 FM(AVB_TD3) \ FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ FM(ASEBRK) \ - FM(MLB_REF) + FM(MLB_REF) \ + FM(VDDQ_AVB0) enum { PINMUX_RESERVED = 0, @@ -5002,7 +5004,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_4 /* RESERVED 3, 2, 1, 0 */ )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -5035,33 +5037,40 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */ { RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { POCCTRL0, + POCCTRL2, TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL0] = { 0xe6060380, }, + [POCCTRL2] = { 0xe6060388, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { - int bit = -EINVAL; + switch (pin) { + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; + return pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; + case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; + return (pin & 0x1f) + 19; - if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) - bit = pin & 0x1f; + case PIN_VDDQ_AVB0: + *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; + return 0; - if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) - bit = (pin & 0x1f) + 19; - - return bit; + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { @@ -5269,7 +5278,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */ [31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */ } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a77990_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index d949ae59c757..298e7a07e493 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -21,7 +21,7 @@ PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -34,7 +34,8 @@ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ - PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -2852,19 +2853,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_26 /* RESERVED 25-0 */ )) }, - { }, + { /* sentinel */ } +}; + +enum ioctrl_regs { + POCCTRL0, + POCCTRL2, + TDSELCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL0] = { 0xe6060380, }, + [POCCTRL2] = { 0xe6060388, }, + [TDSELCTRL] = { 0xe60603c0, }, + { /* sentinel */ } }; + static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { - int bit = -EINVAL; - - *pocctrl = 0xe6060380; + switch (pin) { + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; + return 29 - (pin - RCAR_GP_PIN(3, 0)); - if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) - bit = 29 - (pin - RCAR_GP_PIN(3, 0)); + case PIN_VDDQ_AVB0: + *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; + return 0; - return bit; + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { @@ -3075,15 +3094,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -enum ioctrl_regs { - TDSELCTRL, -}; - -static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, -}; - static const struct pinmux_bias_reg * r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, unsigned int *puen_bit, unsigned int *pud_bit) diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 760c83a8740b..a01bc197d706 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -696,16 +696,8 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(PCIE0_CLKREQ_N), PINMUX_SINGLE(AVB0_PHY_INT), - PINMUX_SINGLE(AVB0_MAGIC), - PINMUX_SINGLE(AVB0_MDC), - PINMUX_SINGLE(AVB0_MDIO), - PINMUX_SINGLE(AVB0_TXCREFCLK), PINMUX_SINGLE(AVB1_PHY_INT), - PINMUX_SINGLE(AVB1_MAGIC), - PINMUX_SINGLE(AVB1_MDC), - PINMUX_SINGLE(AVB1_MDIO), - PINMUX_SINGLE(AVB1_TXCREFCLK), PINMUX_SINGLE(AVB2_AVTP_PPS), PINMUX_SINGLE(AVB2_AVTP_CAPTURE), @@ -3638,7 +3630,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL2_3_2 /* RESERVED 1-0 */ )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -3943,7 +3935,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */ { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -3970,7 +3962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POC8] = { 0xe60690a0, }, [POC9] = { 0xe60698a0, }, [TD1SEL0] = { 0xe6058124, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -4357,7 +4349,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c index 417c357f16b1..16e722a4d18f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -1213,7 +1213,7 @@ static const unsigned int tsn1_avtp_pps_pins[] = { RCAR_GP_PIN(3, 13), }; static const unsigned int tsn1_avtp_pps_mux[] = { - TSN0_AVTP_PPS_MARK, + TSN1_AVTP_PPS_MARK, }; static const unsigned int tsn1_avtp_capture_a_pins[] = { /* TSN1_AVTP_CAPTURE_A */ @@ -1784,7 +1784,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3_2 MOD_SEL1_1_0)) }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -1896,7 +1896,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */ { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */ } }, - { /* sentinel */ }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -1911,7 +1911,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POC1] = { 0xe60508a0, }, [POC3] = { 0xe60518a0, }, [TD0SEL1] = { 0xe6050920, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) @@ -2070,7 +2070,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index bf7fcce2d9c6..acdea6ac1525 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -49,6 +49,12 @@ PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) + /* GPSR0 */ #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) @@ -156,54 +162,54 @@ #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0) /* GPSR4 */ -#define GPSR4_24 FM(AVS1) -#define GPSR4_23 FM(AVS0) -#define GPSR4_22 FM(PCIE1_CLKREQ_N) -#define GPSR4_21 FM(PCIE0_CLKREQ_N) -#define GPSR4_20 FM(TSN0_TXCREFCLK) -#define GPSR4_19 FM(TSN0_TD2) -#define GPSR4_18 FM(TSN0_TD3) -#define GPSR4_17 FM(TSN0_RD2) -#define GPSR4_16 FM(TSN0_RD3) -#define GPSR4_15 FM(TSN0_TD0) -#define GPSR4_14 FM(TSN0_TD1) -#define GPSR4_13 FM(TSN0_RD1) -#define GPSR4_12 FM(TSN0_TXC) -#define GPSR4_11 FM(TSN0_RXC) -#define GPSR4_10 FM(TSN0_RD0) -#define GPSR4_9 FM(TSN0_TX_CTL) -#define GPSR4_8 FM(TSN0_AVTP_PPS0) -#define GPSR4_7 FM(TSN0_RX_CTL) -#define GPSR4_6 FM(TSN0_AVTP_CAPTURE) -#define GPSR4_5 FM(TSN0_AVTP_MATCH) -#define GPSR4_4 FM(TSN0_LINK) -#define GPSR4_3 FM(TSN0_PHY_INT) -#define GPSR4_2 FM(TSN0_AVTP_PPS1) -#define GPSR4_1 FM(TSN0_MDC) -#define GPSR4_0 FM(TSN0_MDIO) +#define GPSR4_24 F_(AVS1, IP3SR4_3_0) +#define GPSR4_23 F_(AVS0, IP2SR4_31_28) +#define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24) +#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) +#define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16) +#define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12) +#define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8) +#define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4) +#define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0) +#define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28) +#define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24) +#define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20) +#define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16) +#define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12) +#define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8) +#define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4) +#define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0) +#define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28) +#define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24) +#define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20) +#define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16) +#define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12) +#define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8) +#define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4) +#define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0) /* GPSR 5 */ -#define GPSR5_20 FM(AVB2_RX_CTL) -#define GPSR5_19 FM(AVB2_TX_CTL) -#define GPSR5_18 FM(AVB2_RXC) -#define GPSR5_17 FM(AVB2_RD0) -#define GPSR5_16 FM(AVB2_TXC) -#define GPSR5_15 FM(AVB2_TD0) -#define GPSR5_14 FM(AVB2_RD1) -#define GPSR5_13 FM(AVB2_RD2) -#define GPSR5_12 FM(AVB2_TD1) -#define GPSR5_11 FM(AVB2_TD2) -#define GPSR5_10 FM(AVB2_MDIO) -#define GPSR5_9 FM(AVB2_RD3) -#define GPSR5_8 FM(AVB2_TD3) -#define GPSR5_7 FM(AVB2_TXCREFCLK) -#define GPSR5_6 FM(AVB2_MDC) -#define GPSR5_5 FM(AVB2_MAGIC) -#define GPSR5_4 FM(AVB2_PHY_INT) -#define GPSR5_3 FM(AVB2_LINK) -#define GPSR5_2 FM(AVB2_AVTP_MATCH) -#define GPSR5_1 FM(AVB2_AVTP_CAPTURE) -#define GPSR5_0 FM(AVB2_AVTP_PPS) +#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16) +#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12) +#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8) +#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4) +#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0) +#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28) +#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24) +#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20) +#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16) +#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12) +#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8) +#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4) +#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0) +#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28) +#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24) +#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20) +#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16) +#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12) +#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8) +#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4) +#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0) /* GPSR 6 */ #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) @@ -268,209 +274,271 @@ #define GPSR8_0 F_(SCL0, IP0SR8_3_0) /* SR0 */ -/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR1 */ -/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR2 */ -/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR3 */ -/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR4 */ +/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* SR5 */ +/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR6 */ -/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR7 */ -/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* SR8 */ -/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) - -/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ +#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ GPSR3_29 \ @@ -542,6 +610,24 @@ FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \ FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \ \ +FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \ +FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ +FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ +FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ +FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ +FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ +FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \ +FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ +\ +FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ +FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ +FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ +FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ +FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ +FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ +FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ +FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \ +\ FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \ FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \ FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \ @@ -569,54 +655,6 @@ FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \ FM(IP0SR8_27_24) IP0SR8_27_24 \ FM(IP0SR8_31_28) IP0SR8_31_28 -/* MOD_SEL4 */ /* 0 */ /* 1 */ -#define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1) -#define MOD_SEL4_18 FM(SEL_TSN0_TD3_0) FM(SEL_TSN0_TD3_1) -#define MOD_SEL4_15 FM(SEL_TSN0_TD0_0) FM(SEL_TSN0_TD0_1) -#define MOD_SEL4_14 FM(SEL_TSN0_TD1_0) FM(SEL_TSN0_TD1_1) -#define MOD_SEL4_12 FM(SEL_TSN0_TXC_0) FM(SEL_TSN0_TXC_1) -#define MOD_SEL4_9 FM(SEL_TSN0_TX_CTL_0) FM(SEL_TSN0_TX_CTL_1) -#define MOD_SEL4_8 FM(SEL_TSN0_AVTP_PPS0_0) FM(SEL_TSN0_AVTP_PPS0_1) -#define MOD_SEL4_5 FM(SEL_TSN0_AVTP_MATCH_0) FM(SEL_TSN0_AVTP_MATCH_1) -#define MOD_SEL4_2 FM(SEL_TSN0_AVTP_PPS1_0) FM(SEL_TSN0_AVTP_PPS1_1) -#define MOD_SEL4_1 FM(SEL_TSN0_MDC_0) FM(SEL_TSN0_MDC_1) - -/* MOD_SEL5 */ /* 0 */ /* 1 */ -#define MOD_SEL5_19 FM(SEL_AVB2_TX_CTL_0) FM(SEL_AVB2_TX_CTL_1) -#define MOD_SEL5_16 FM(SEL_AVB2_TXC_0) FM(SEL_AVB2_TXC_1) -#define MOD_SEL5_15 FM(SEL_AVB2_TD0_0) FM(SEL_AVB2_TD0_1) -#define MOD_SEL5_12 FM(SEL_AVB2_TD1_0) FM(SEL_AVB2_TD1_1) -#define MOD_SEL5_11 FM(SEL_AVB2_TD2_0) FM(SEL_AVB2_TD2_1) -#define MOD_SEL5_8 FM(SEL_AVB2_TD3_0) FM(SEL_AVB2_TD3_1) -#define MOD_SEL5_6 FM(SEL_AVB2_MDC_0) FM(SEL_AVB2_MDC_1) -#define MOD_SEL5_5 FM(SEL_AVB2_MAGIC_0) FM(SEL_AVB2_MAGIC_1) -#define MOD_SEL5_2 FM(SEL_AVB2_AVTP_MATCH_0) FM(SEL_AVB2_AVTP_MATCH_1) -#define MOD_SEL5_0 FM(SEL_AVB2_AVTP_PPS_0) FM(SEL_AVB2_AVTP_PPS_1) - -/* MOD_SEL6 */ /* 0 */ /* 1 */ -#define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1) -#define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1) -#define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1) -#define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1) -#define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1) -#define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1) -#define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1) -#define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1) -#define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1) -#define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1) - -/* MOD_SEL7 */ /* 0 */ /* 1 */ -#define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1) -#define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1) -#define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1) -#define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1) -#define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1) -#define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1) -#define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1) -#define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1) -#define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1) -#define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1) - /* MOD_SEL8 */ /* 0 */ /* 1 */ #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1) #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1) @@ -633,26 +671,18 @@ FM(IP0SR8_31_28) IP0SR8_31_28 #define PINMUX_MOD_SELS \ \ -MOD_SEL4_19 MOD_SEL5_19 \ -MOD_SEL4_18 MOD_SEL6_18 \ - \ - MOD_SEL5_16 MOD_SEL6_16 MOD_SEL7_16 \ -MOD_SEL4_15 MOD_SEL5_15 MOD_SEL7_15 \ -MOD_SEL4_14 \ - MOD_SEL6_13 MOD_SEL7_13 \ -MOD_SEL4_12 MOD_SEL5_12 MOD_SEL6_12 \ - MOD_SEL5_11 MOD_SEL7_11 MOD_SEL8_11 \ - MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \ -MOD_SEL4_9 MOD_SEL8_9 \ -MOD_SEL4_8 MOD_SEL5_8 MOD_SEL8_8 \ - MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \ - MOD_SEL5_6 MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \ -MOD_SEL4_5 MOD_SEL5_5 MOD_SEL6_5 MOD_SEL8_5 \ - MOD_SEL8_4 \ - MOD_SEL7_3 MOD_SEL8_3 \ -MOD_SEL4_2 MOD_SEL5_2 MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \ -MOD_SEL4_1 MOD_SEL6_1 MOD_SEL8_1 \ - MOD_SEL5_0 MOD_SEL7_0 MOD_SEL8_0 +MOD_SEL8_11 \ +MOD_SEL8_10 \ +MOD_SEL8_9 \ +MOD_SEL8_8 \ +MOD_SEL8_7 \ +MOD_SEL8_6 \ +MOD_SEL8_5 \ +MOD_SEL8_4 \ +MOD_SEL8_3 \ +MOD_SEL8_2 \ +MOD_SEL8_1 \ +MOD_SEL8_0 enum { PINMUX_RESERVED = 0, @@ -686,61 +716,8 @@ enum { static const u16 pinmux_data[] = { PINMUX_DATA_GP_ALL(), - PINMUX_SINGLE(AVS1), - PINMUX_SINGLE(AVS0), - PINMUX_SINGLE(PCIE1_CLKREQ_N), - PINMUX_SINGLE(PCIE0_CLKREQ_N), - - /* TSN0 without MODSEL4 */ - PINMUX_SINGLE(TSN0_TXCREFCLK), - PINMUX_SINGLE(TSN0_RD2), - PINMUX_SINGLE(TSN0_RD3), - PINMUX_SINGLE(TSN0_RD1), - PINMUX_SINGLE(TSN0_RXC), - PINMUX_SINGLE(TSN0_RD0), - PINMUX_SINGLE(TSN0_RX_CTL), - PINMUX_SINGLE(TSN0_AVTP_CAPTURE), - PINMUX_SINGLE(TSN0_LINK), - PINMUX_SINGLE(TSN0_PHY_INT), - PINMUX_SINGLE(TSN0_MDIO), - /* TSN0 with MODSEL4 */ - PINMUX_IPSR_NOGM(0, TSN0_TD2, SEL_TSN0_TD2_1), - PINMUX_IPSR_NOGM(0, TSN0_TD3, SEL_TSN0_TD3_1), - PINMUX_IPSR_NOGM(0, TSN0_TD0, SEL_TSN0_TD0_1), - PINMUX_IPSR_NOGM(0, TSN0_TD1, SEL_TSN0_TD1_1), - PINMUX_IPSR_NOGM(0, TSN0_TXC, SEL_TSN0_TXC_1), - PINMUX_IPSR_NOGM(0, TSN0_TX_CTL, SEL_TSN0_TX_CTL_1), - PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0, SEL_TSN0_AVTP_PPS0_1), - PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH, SEL_TSN0_AVTP_MATCH_1), - PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1), - PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1), - - /* TSN0 without MODSEL5 */ - PINMUX_SINGLE(AVB2_RX_CTL), - PINMUX_SINGLE(AVB2_RXC), - PINMUX_SINGLE(AVB2_RD0), - PINMUX_SINGLE(AVB2_RD1), - PINMUX_SINGLE(AVB2_RD2), - PINMUX_SINGLE(AVB2_MDIO), - PINMUX_SINGLE(AVB2_RD3), - PINMUX_SINGLE(AVB2_TXCREFCLK), - PINMUX_SINGLE(AVB2_PHY_INT), - PINMUX_SINGLE(AVB2_LINK), - PINMUX_SINGLE(AVB2_AVTP_CAPTURE), - /* TSN0 with MODSEL5 */ - PINMUX_IPSR_NOGM(0, AVB2_TX_CTL, SEL_AVB2_TX_CTL_1), - PINMUX_IPSR_NOGM(0, AVB2_TXC, SEL_AVB2_TXC_1), - PINMUX_IPSR_NOGM(0, AVB2_TD0, SEL_AVB2_TD0_1), - PINMUX_IPSR_NOGM(0, AVB2_TD1, SEL_AVB2_TD1_1), - PINMUX_IPSR_NOGM(0, AVB2_TD2, SEL_AVB2_TD2_1), - PINMUX_IPSR_NOGM(0, AVB2_TD3, SEL_AVB2_TD3_1), - PINMUX_IPSR_NOGM(0, AVB2_MDC, SEL_AVB2_MDC_1), - PINMUX_IPSR_NOGM(0, AVB2_MAGIC, SEL_AVB2_MAGIC_1), - PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH, SEL_AVB2_AVTP_MATCH_1), - PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS, SEL_AVB2_AVTP_PPS_1), - /* IP0SR0 */ - PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B), + PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A), PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), @@ -1006,7 +983,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT), PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT), - PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_A), + PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A), PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X), PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), @@ -1029,26 +1006,86 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N), PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N), + /* IP0SR4 */ + PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO), + PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC), + PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1), + PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT), + PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK), + PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL), + + /* IP1SR4 */ + PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0), + PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL), + PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0), + PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC), + PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC), + PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1), + PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1), + PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0), + + /* IP2SR4 */ + PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3), + PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2), + PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3), + PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2), + PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK), + PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N), + PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N), + PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0), + + /* IP3SR4 */ + PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1), + + /* IP0SR5 */ + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS), + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK), + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT), + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC), + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC), + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK), + + /* IP1SR5 */ + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3), + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3), + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO), + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2), + PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1), + PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2), + PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1), + PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0), + + /* IP2SR5 */ + PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC), + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0), + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC), + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL), + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL), + /* IP0SR6 */ PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO), - PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1), + PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC), - PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1), + PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC), PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), - PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1), - PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0), + PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), - PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1), - PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0), + PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), + PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), - PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1), - PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0), + PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), /* IP1SR6 */ PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), @@ -1057,17 +1094,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), - PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1), - PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0), + PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), + PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), - PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1), - PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0), + PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), + PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), - PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1), - PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0), + PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), + PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), @@ -1076,14 +1113,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), /* IP2SR6 */ - PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1), - PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0), + PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), + PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), - PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1), - PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0), + PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), + PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), @@ -1091,29 +1128,29 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), /* IP0SR7 */ - PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1), - PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0), + PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), + PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), - PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1), - PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0), - PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0), + PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), + PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), - PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1), - PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0), + PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), + PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), - PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1), - PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0), + PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), + PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), - PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1), - PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0), + PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), + PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), /* IP1SR7 */ PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), @@ -1121,24 +1158,24 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), - PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1), + PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), - PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1), - PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0), + PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), + PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), - PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1), + PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), - PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1), - PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0), + PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), + PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), /* IP2SR7 */ - PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1), - PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0), + PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), + PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), @@ -1190,10 +1227,28 @@ static const u16 pinmux_data[] = { */ enum { GP_ASSIGN_LAST(), + NOGP_ALL(), }; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), +}; + +/* - AUDIO CLOCK ----------------------------------------- */ +static const unsigned int audio_clkin_pins[] = { + /* CLK IN */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int audio_clkin_mux[] = { + AUDIO_CLKIN_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLK OUT */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, }; /* - AVB0 ------------------------------------------------ */ @@ -2329,6 +2384,22 @@ static const unsigned int scif_clk_mux[] = { SCIF_CLK_MARK, }; +/* - SSI ------------------------------------------------- */ +static const unsigned int ssi_data_pins[] = { + /* SSI_SD */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int ssi_data_mux[] = { + SSI_SD_MARK, +}; +static const unsigned int ssi_ctrl_pins[] = { + /* SSI_SCK, SSI_WS */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; +static const unsigned int ssi_ctrl_mux[] = { + SSI_SCK_MARK, SSI_WS_MARK, +}; + /* - TPU ------------------------------------------------------------------- */ static const unsigned int tpu_to0_pins[] = { /* TPU0TO0 */ @@ -2461,6 +2532,9 @@ static const unsigned int tsn0_avtp_match_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clkin), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), @@ -2621,6 +2695,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif4_ctrl), SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(ssi_data), + SH_PFC_PIN_GROUP(ssi_ctrl), + SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */ SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */ SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */ @@ -2640,6 +2717,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tsn0_avtp_match), }; +static const char * const audio_clk_groups[] = { + "audio_clkin", + "audio_clkout", +}; + static const char * const avb0_groups[] = { "avb0_link", "avb0_magic", @@ -2933,6 +3015,11 @@ static const char * const scif_clk_groups[] = { "scif_clk", }; +static const char * const ssi_groups[] = { + "ssi_data", + "ssi_ctrl", +}; + static const char * const tpu_groups[] = { /* suffix might be updated */ "tpu_to0", @@ -2957,6 +3044,8 @@ static const char * const tsn0_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), SH_PFC_FUNCTION(avb2), @@ -3014,6 +3103,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(tsn0), @@ -3419,6 +3510,82 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3SR3_7_4 IP3SR3_3_0)) }, + { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32, + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + IP0SR4_31_28 + IP0SR4_27_24 + IP0SR4_23_20 + IP0SR4_19_16 + IP0SR4_15_12 + IP0SR4_11_8 + IP0SR4_7_4 + IP0SR4_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32, + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + IP1SR4_31_28 + IP1SR4_27_24 + IP1SR4_23_20 + IP1SR4_19_16 + IP1SR4_15_12 + IP1SR4_11_8 + IP1SR4_7_4 + IP1SR4_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32, + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + IP2SR4_31_28 + IP2SR4_27_24 + IP2SR4_23_20 + IP2SR4_19_16 + IP2SR4_15_12 + IP2SR4_11_8 + IP2SR4_7_4 + IP2SR4_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32, + GROUP(-28, 4), + GROUP( + /* IP3SR4_31_4 RESERVED */ + IP3SR4_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32, + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + IP0SR5_31_28 + IP0SR5_27_24 + IP0SR5_23_20 + IP0SR5_19_16 + IP0SR5_15_12 + IP0SR5_11_8 + IP0SR5_7_4 + IP0SR5_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32, + GROUP(4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + IP1SR5_31_28 + IP1SR5_27_24 + IP1SR5_23_20 + IP1SR5_19_16 + IP1SR5_15_12 + IP1SR5_11_8 + IP1SR5_7_4 + IP1SR5_3_0)) + }, + { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32, + GROUP(-12, 4, 4, 4, 4, 4), + GROUP( + /* IP2SR5_31_20 RESERVED */ + IP2SR5_19_16 + IP2SR5_15_12 + IP2SR5_11_8 + IP2SR5_7_4 + IP2SR5_3_0)) + }, { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP( IP0SR6_31_28 IP0SR6_27_24 @@ -3505,95 +3672,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32, - GROUP(-12, 1, 1, -2, 1, 1, -1, 1, -2, 1, 1, -2, 1, - -2, 1, 1, -1), - GROUP( - /* RESERVED 31-20 */ - MOD_SEL4_19 - MOD_SEL4_18 - /* RESERVED 17-16 */ - MOD_SEL4_15 - MOD_SEL4_14 - /* RESERVED 13 */ - MOD_SEL4_12 - /* RESERVED 11-10 */ - MOD_SEL4_9 - MOD_SEL4_8 - /* RESERVED 7-6 */ - MOD_SEL4_5 - /* RESERVED 4-3 */ - MOD_SEL4_2 - MOD_SEL4_1 - /* RESERVED 0 */ - )) - }, - { PINMUX_CFG_REG_VAR("MOD_SEL5", 0xE6060900, 32, - GROUP(-12, 1, -2, 1, 1, -2, 1, 1, -2, 1, -1, - 1, 1, -2, 1, -1, 1), - GROUP( - /* RESERVED 31-20 */ - MOD_SEL5_19 - /* RESERVED 18-17 */ - MOD_SEL5_16 - MOD_SEL5_15 - /* RESERVED 14-13 */ - MOD_SEL5_12 - MOD_SEL5_11 - /* RESERVED 10-9 */ - MOD_SEL5_8 - /* RESERVED 7 */ - MOD_SEL5_6 - MOD_SEL5_5 - /* RESERVED 4-3 */ - MOD_SEL5_2 - /* RESERVED 1 */ - MOD_SEL5_0)) - }, - { PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32, - GROUP(-13, 1, -1, 1, -2, 1, 1, - -1, 1, -2, 1, 1, 1, -2, 1, 1, -1), - GROUP( - /* RESERVED 31-19 */ - MOD_SEL6_18 - /* RESERVED 17 */ - MOD_SEL6_16 - /* RESERVED 15-14 */ - MOD_SEL6_13 - MOD_SEL6_12 - /* RESERVED 11 */ - MOD_SEL6_10 - /* RESERVED 9-8 */ - MOD_SEL6_7 - MOD_SEL6_6 - MOD_SEL6_5 - /* RESERVED 4-3 */ - MOD_SEL6_2 - MOD_SEL6_1 - /* RESERVED 0 */ - )) - }, - { PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32, - GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1, - -2, 1, 1, -1, 1), - GROUP( - /* RESERVED 31-17 */ - MOD_SEL7_16 - MOD_SEL7_15 - /* RESERVED 14 */ - MOD_SEL7_13 - /* RESERVED 12 */ - MOD_SEL7_11 - MOD_SEL7_10 - /* RESERVED 9-8 */ - MOD_SEL7_7 - MOD_SEL7_6 - /* RESERVED 5-4 */ - MOD_SEL7_3 - MOD_SEL7_2 - /* RESERVED 1 */ - MOD_SEL7_0)) - }, { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32, GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( @@ -3611,7 +3689,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL8_1 MOD_SEL8_0)) }, - { }, + { /* sentinel */ } }; static const struct pinmux_drive_reg pinmux_drive_regs[] = { @@ -3873,7 +3951,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */ { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */ } }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -3896,30 +3974,49 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POC6] = { 0xE60610A0, }, [POC7] = { 0xE60618A0, }, [POC8] = { 0xE60680A0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[POC0].reg; - if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18)) + switch (pin) { + case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): + *pocctrl = pinmux_ioctrl_regs[POC0].reg; return bit; - *pocctrl = pinmux_ioctrl_regs[POC1].reg; - if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) + case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22): + *pocctrl = pinmux_ioctrl_regs[POC1].reg; return bit; - *pocctrl = pinmux_ioctrl_regs[POC3].reg; - if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12)) + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): + *pocctrl = pinmux_ioctrl_regs[POC3].reg; return bit; - *pocctrl = pinmux_ioctrl_regs[POC8].reg; - if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13)) + case PIN_VDDQ_TSN0: + *pocctrl = pinmux_ioctrl_regs[POC4].reg; + return 0; + + case PIN_VDDQ_AVB2: + *pocctrl = pinmux_ioctrl_regs[POC5].reg; + return 0; + + case PIN_VDDQ_AVB1: + *pocctrl = pinmux_ioctrl_regs[POC6].reg; + return 0; + + case PIN_VDDQ_AVB0: + *pocctrl = pinmux_ioctrl_regs[POC7].reg; + return 0; + + case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13): + *pocctrl = pinmux_ioctrl_regs[POC8].reg; return bit; - return -EINVAL; + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { @@ -4229,7 +4326,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [30] = SH_PFC_PIN_NONE, [31] = SH_PFC_PIN_NONE, } }, - { /* sentinel */ }, + { /* sentinel */ } }; static const struct sh_pfc_soc_operations r8a779g0_pin_ops = { diff --git a/drivers/pinctrl/renesas/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c index 19735746b1bb..640564db2c0b 100644 --- a/drivers/pinctrl/renesas/pfc-sh7203.c +++ b/drivers/pinctrl/renesas/pfc-sh7203.c @@ -1509,7 +1509,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -1555,7 +1555,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7203_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c index 30096925a70c..8417c4243dda 100644 --- a/drivers/pinctrl/renesas/pfc-sh7264.c +++ b/drivers/pinctrl/renesas/pfc-sh7264.c @@ -2031,7 +2031,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PK1_IN, PK1_OUT, PK0_IN, PK0_OUT )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2109,7 +2109,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA )) }, - { } + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7264_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c index f59f558d75ae..3569093f17ae 100644 --- a/drivers/pinctrl/renesas/pfc-sh7269.c +++ b/drivers/pinctrl/renesas/pfc-sh7269.c @@ -2749,8 +2749,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PJ1_IN, PJ1_OUT, PJ0_IN, PJ0_OUT )) }, - - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2828,8 +2827,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA )) }, - - { } + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7269_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c index 4f54dfd5a967..ca5adf2095be 100644 --- a/drivers/pinctrl/renesas/pfc-sh73a0.c +++ b/drivers/pinctrl/renesas/pfc-sh73a0.c @@ -3876,7 +3876,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -3980,7 +3980,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_irq pinmux_irqs[] = { diff --git a/drivers/pinctrl/renesas/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c index 6eedcc5bbb4d..91434743fb1c 100644 --- a/drivers/pinctrl/renesas/pfc-sh7720.c +++ b/drivers/pinctrl/renesas/pfc-sh7720.c @@ -1103,7 +1103,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PTV1_FN, PTV1_OUT, 0, PTV1_IN, PTV0_FN, PTV0_OUT, 0, PTV0_IN )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -1179,7 +1179,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, 0, PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7720_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c index 4b82ac2c5e91..54b4625b52cf 100644 --- a/drivers/pinctrl/renesas/pfc-sh7722.c +++ b/drivers/pinctrl/renesas/pfc-sh7722.c @@ -1585,7 +1585,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSELB8_RGB, MSELB8_SYS, /* RESERVED [8] */ )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -1681,7 +1681,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7722_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c index 95344281966e..c1abdec9bf1d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7723.c +++ b/drivers/pinctrl/renesas/pfc-sh7723.c @@ -1784,7 +1784,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0, PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -1880,7 +1880,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7723_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c index 26517ad26a0f..5148a3460cc6 100644 --- a/drivers/pinctrl/renesas/pfc-sh7724.c +++ b/drivers/pinctrl/renesas/pfc-sh7724.c @@ -2059,7 +2059,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PSE1_0, PSE1_1, PSE0_0, PSE0_1)) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2155,7 +2155,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7724_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c index 106a500ad13d..a0a5d8b94086 100644 --- a/drivers/pinctrl/renesas/pfc-sh7734.c +++ b/drivers/pinctrl/renesas/pfc-sh7734.c @@ -2366,7 +2366,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_IN, GP_5_1_OUT, GP_5_0_IN, GP_5_0_OUT )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2383,7 +2383,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7734_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7757.c b/drivers/pinctrl/renesas/pfc-sh7757.c index 0d7857d7efef..817b22c3e639 100644 --- a/drivers/pinctrl/renesas/pfc-sh7757.c +++ b/drivers/pinctrl/renesas/pfc-sh7757.c @@ -2089,7 +2089,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PS8_8_FN1, PS8_8_FN2, /* RESERVED [8] */ )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -2197,7 +2197,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7757_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7785.c b/drivers/pinctrl/renesas/pfc-sh7785.c index 126b663bb6eb..0b6fbbac7c6d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7785.c +++ b/drivers/pinctrl/renesas/pfc-sh7785.c @@ -1168,7 +1168,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { P2MSEL1_0, P2MSEL1_1, P2MSEL0_0, P2MSEL0_1 )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -1236,7 +1236,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, 0, 0, PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7785_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-sh7786.c b/drivers/pinctrl/renesas/pfc-sh7786.c index f09f4a769010..a1ff39c5424d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7786.c +++ b/drivers/pinctrl/renesas/pfc-sh7786.c @@ -747,7 +747,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { P2MSEL1_0, P2MSEL1_1, P2MSEL0_0, P2MSEL0_1 )) }, - {} + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -787,7 +787,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info sh7786_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-shx3.c b/drivers/pinctrl/renesas/pfc-shx3.c index 96a65d83774f..e2ba5e3b9ec3 100644 --- a/drivers/pinctrl/renesas/pfc-shx3.c +++ b/drivers/pinctrl/renesas/pfc-shx3.c @@ -502,7 +502,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PH1_FN, PH1_OUT, PH1_IN, 0, PH0_FN, PH0_OUT, PH0_IN, 0, )) }, - { }, + { /* sentinel */ } }; static const struct pinmux_data_reg pinmux_data_regs[] = { @@ -538,7 +538,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, PH5_DATA, PH4_DATA, PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, )) }, - { }, + { /* sentinel */ } }; const struct sh_pfc_soc_info shx3_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 48173355a040..68c7af5d86bc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -1388,7 +1388,7 @@ static const struct of_device_id rza1_pinctrl_of_match[] = { .compatible = "renesas,r7s72102-ports", .data = &rza1l_pmx_conf, }, - { } + { /* sentinel */ } }; static struct platform_driver rza1_pinctrl_driver = { diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c index d73741651419..374b9f281324 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzn1.c +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c @@ -931,7 +931,7 @@ static int rzn1_pinctrl_remove(struct platform_device *pdev) static const struct of_device_id rzn1_pinctrl_match[] = { { .compatible = "renesas,rzn1-pinctrl", }, - {} + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match); diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index b74147800319..4d9d58fc1356 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -40,10 +40,6 @@ struct sh_pfc_pinctrl { struct pinctrl_pin_desc *pins; struct sh_pfc_pin_config *configs; - - const char *func_prop_name; - const char *groups_prop_name; - const char *pins_prop_name; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) @@ -120,27 +116,10 @@ static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, const char *pin; int ret; - /* Support both the old Renesas-specific properties and the new standard - * properties. Mixing old and new properties isn't allowed, neither - * inside a subnode nor across subnodes. - */ - if (!pmx->func_prop_name) { - if (of_find_property(np, "groups", NULL) || - of_find_property(np, "pins", NULL)) { - pmx->func_prop_name = "function"; - pmx->groups_prop_name = "groups"; - pmx->pins_prop_name = "pins"; - } else { - pmx->func_prop_name = "renesas,function"; - pmx->groups_prop_name = "renesas,groups"; - pmx->pins_prop_name = "renesas,pins"; - } - } - /* Parse the function and configuration properties. At least a function * or one configuration must be specified. */ - ret = of_property_read_string(np, pmx->func_prop_name, &function); + ret = of_property_read_string(np, "function", &function); if (ret < 0 && ret != -EINVAL) { dev_err(dev, "Invalid function in DT\n"); return ret; @@ -158,7 +137,7 @@ static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, } /* Count the number of pins and groups and reallocate mappings. */ - ret = of_property_count_strings(np, pmx->pins_prop_name); + ret = of_property_count_strings(np, "pins"); if (ret == -EINVAL) { num_pins = 0; } else if (ret < 0) { @@ -168,7 +147,7 @@ static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, num_pins = ret; } - ret = of_property_count_strings(np, pmx->groups_prop_name); + ret = of_property_count_strings(np, "groups"); if (ret == -EINVAL) { num_groups = 0; } else if (ret < 0) { @@ -199,7 +178,7 @@ static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, *num_maps = nmaps; /* Iterate over pins and groups and create the mappings. */ - of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { + of_property_for_each_string(np, "groups", prop, group) { if (function) { maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; maps[idx].data.mux.group = group; @@ -223,7 +202,7 @@ static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, goto done; } - of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { + of_property_for_each_string(np, "pins", prop, pin) { ret = sh_pfc_map_add_config(&maps[idx], pin, PIN_MAP_TYPE_CONFIGS_PIN, configs, num_configs); @@ -580,7 +559,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; case PIN_CONFIG_POWER_SOURCE: - return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; + return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; default: return false; @@ -633,7 +612,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, case PIN_CONFIG_POWER_SOURCE: { int idx = sh_pfc_get_pin_index(pfc, _pin); const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - unsigned int lower_voltage; + unsigned int mode, lo, hi; u32 pocctrl, val; int bit; @@ -646,10 +625,11 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, val = sh_pfc_read(pfc, pocctrl); - lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ? - 2500 : 1800; + mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; + lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; + hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; - arg = (val & BIT(bit)) ? 3300 : lower_voltage; + arg = (val & BIT(bit)) ? hi : lo; break; } @@ -705,7 +685,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, unsigned int mV = pinconf_to_config_argument(configs[i]); int idx = sh_pfc_get_pin_index(pfc, _pin); const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - unsigned int lower_voltage; + unsigned int mode, lo, hi; u32 pocctrl, val; int bit; @@ -716,15 +696,16 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; - lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ? - 2500 : 1800; + mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; + lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; + hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; - if (mV != lower_voltage && mV != 3300) + if (mV != lo && mV != hi) return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); val = sh_pfc_read(pfc, pocctrl); - if (mV == 3300) + if (mV == hi) val |= BIT(bit); else val &= ~BIT(bit); diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 0fcb29ab0c84..8dc7a66009ad 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -29,16 +29,13 @@ enum { #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ SH_PFC_PIN_CFG_PULL_DOWN) -#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) -#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) -#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) -#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4) -#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ - SH_PFC_PIN_VOLTAGE_18_33) -#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ - SH_PFC_PIN_VOLTAGE_25_33) +#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6) #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) @@ -314,7 +311,6 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a77950_pinmux_info; extern const struct sh_pfc_soc_info r8a77951_pinmux_info; extern const struct sh_pfc_soc_info r8a77960_pinmux_info; extern const struct sh_pfc_soc_info r8a77961_pinmux_info; |