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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-07-31 09:21:08 +0300
committerLinus Walleij <linus.walleij@linaro.org>2017-08-14 16:01:00 +0300
commit7f6ee0a5791bf78b01232c290ce548159ceebfe2 (patch)
treefbba86f66d0d373d86c27bfd90daa1d0b1282440 /drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
parente3829d15460feb884805012c72ec4a17402822eb (diff)
downloadlinux-7f6ee0a5791bf78b01232c290ce548159ceebfe2.tar.xz
pinctrl: uniphier: clean up GPIO port muxing
There are a bunch of GPIO muxing data, but most of them are actually unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges" DT properties. Tables that contain a set of GPIO pins are still needed for the named mapping by "gpio-ranges-group-names". This is a much cleaner way for UniPhier SoC family where GPIO numbers are not straight mapped to pin numbers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c')
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c272
1 files changed, 38 insertions, 234 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 37deaf615dcf..f0221e93aa25 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -532,67 +532,28 @@ static const unsigned usb1_pins[] = {43, 44};
static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {114, 115};
static const int usb2_muxvals[] = {1, 1};
-static const unsigned port_range0_pins[] = {
- 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
- 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
- 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */
- 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */
- 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */
- 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */
- 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */
- 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */
- 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */
- 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */
- 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */
- 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
- 47, 127, 20, 56, 22, /* PORT120-124 */
+static const unsigned int gpio_range0_pins[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
+ 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */
+ 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */
+ 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */
+ 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */
+ 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */
+ 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */
+ 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */
+ 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */
+ 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */
+ 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
+ 47, 127, 20, 56, 22, /* PORT120-124 */
};
-static const int port_range0_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
- 15, 15, 15, 15, 15, /* PORT120-124 */
+static const unsigned int gpio_range1_pins[] = {
+ 116, 117, /* PORT130-131 */
};
-static const unsigned port_range1_pins[] = {
- 116, 117, /* PORT130-131 */
-};
-static const int port_range1_muxvals[] = {
- 15, 15, /* PORT130-131 */
-};
-static const unsigned port_range2_pins[] = {
- 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
-};
-static const int port_range2_muxvals[] = {
- 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
-};
-static const unsigned port_range3_pins[] = {
- 23, /* PORT166 */
-};
-static const int port_range3_muxvals[] = {
- 15, /* PORT166 */
-};
-static const unsigned xirq_range0_pins[] = {
- 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
- 82, 87, 88, 50, 51, /* XIRQ8-12 */
-};
-static const int xirq_range0_muxvals[] = {
- 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
- 14, 14, 14, 14, 14, /* XIRQ8-12 */
-};
-static const unsigned xirq_range1_pins[] = {
- 52, 58, /* XIRQ14-15 */
-};
-static const int xirq_range1_muxvals[] = {
- 14, 14, /* XIRQ14-15 */
+static const unsigned int gpio_range2_pins[] = {
+ 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
+ 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
+ 82, 87, 88, 50, 51, 23, 52, 58, /* XIRQ8-12, PORT165, XIRQ14-15 */
};
static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
@@ -620,139 +581,9 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
- UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
- UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
@@ -777,46 +608,6 @@ static const char * const uart3_groups[] = {"uart3"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
-static const char * const port_groups[] = {
- "port00", "port01", "port02", "port03",
- "port04", "port05", "port06", "port07",
- "port10", "port11", "port12", "port13",
- "port14", "port15", "port16", "port17",
- "port20", "port21", "port22", "port23",
- "port24", "port25", "port26", "port27",
- "port30", "port31", "port32", "port33",
- "port34", "port35", "port36", "port37",
- "port40", "port41", "port42", "port43",
- "port44", "port45", "port46", "port47",
- "port50", "port51", "port52", "port53",
- "port54", "port55", "port56", "port57",
- "port60", "port61", "port62", "port63",
- "port64", "port65", "port66", "port67",
- "port70", "port71", "port72", "port73",
- "port74", "port75", "port76", "port77",
- "port80", "port81", "port82", "port83",
- "port84", "port85", "port86", "port87",
- "port90", "port91", "port92", "port93",
- "port94", "port95", "port96", "port97",
- "port100", "port101", "port102", "port103",
- "port104", "port105", "port106", "port107",
- "port110", "port111", "port112", "port113",
- "port114", "port115", "port116", "port117",
- "port120", "port121", "port122", "port123",
- "port124", "port125", "port126", "port127",
- "port130", "port131", "port132", "port133",
- "port134", "port135", "port136", "port137",
- "port140", "port141", "port142", "port143",
- "port144", "port145", "port146", "port147",
- /* port150-164 missing */
- /* none */ "port165",
-};
-static const char * const xirq_groups[] = {
- "xirq0", "xirq1", "xirq2", "xirq3",
- "xirq4", "xirq5", "xirq6", "xirq7",
- "xirq8", "xirq9", "xirq10", "xirq11",
- "xirq12", /* none*/ "xirq14", "xirq15",
-};
static const struct uniphier_pinmux_function uniphier_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
@@ -836,10 +627,22 @@ static const struct uniphier_pinmux_function uniphier_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(port),
- UNIPHIER_PINMUX_FUNCTION(xirq),
};
+static int uniphier_sld8_get_gpio_muxval(unsigned int pin,
+ unsigned int gpio_offset)
+{
+ switch (gpio_offset) {
+ case 120 ... 127: /* XIRQ0-XIRQ7 */
+ return 0;
+ case 128 ... 132: /* XIRQ8-12 */
+ case 134 ... 135: /* XIRQ14-15 */
+ return 14;
+ default:
+ return 15;
+ }
+}
+
static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = {
.pins = uniphier_sld8_pins,
.npins = ARRAY_SIZE(uniphier_sld8_pins),
@@ -847,6 +650,7 @@ static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = {
.groups_count = ARRAY_SIZE(uniphier_sld8_groups),
.functions = uniphier_sld8_functions,
.functions_count = ARRAY_SIZE(uniphier_sld8_functions),
+ .get_gpio_muxval = uniphier_sld8_get_gpio_muxval,
.caps = 0,
};