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| author | David S. Miller <davem@davemloft.net> | 2021-03-26 01:31:22 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-03-26 01:31:22 +0300 |
| commit | efd13b71a3fa31413f8d15342e01d44b60b0a432 (patch) | |
| tree | 2ed1b299e25538c5a60485a1047507b49d3e0ecf /drivers/platform/x86/Kconfig | |
| parent | 84c7f6c33f42a12eb036ebf0f0e3670799304120 (diff) | |
| parent | 002322402dafd846c424ffa9240a937f49b48c42 (diff) | |
| download | linux-efd13b71a3fa31413f8d15342e01d44b60b0a432.tar.xz | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/platform/x86/Kconfig')
| -rw-r--r-- | drivers/platform/x86/Kconfig | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index ad4e630e73e2..461ec61530eb 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1173,15 +1173,20 @@ config INTEL_PMC_CORE depends on PCI help The Intel Platform Controller Hub for Intel Core SoCs provides access - to Power Management Controller registers via a PCI interface. This + to Power Management Controller registers via various interfaces. This driver can utilize debugging capabilities and supported features as - exposed by the Power Management Controller. + exposed by the Power Management Controller. It also may perform some + tasks in the PMC in order to enable transition into the SLPS0 state. + It should be selected on all Intel platforms supported by the driver. Supported features: - SLP_S0_RESIDENCY counter - PCH IP Power Gating status - - LTR Ignore + - LTR Ignore / LTR Show - MPHY/PLL gating status (Sunrisepoint PCH only) + - SLPS0 Debug registers (Cannonlake/Icelake PCH) + - Low Power Mode registers (Tigerlake and beyond) + - PMC quirks as needed to enable SLPS0/S0ix config INTEL_PMT_CLASS tristate |