diff options
author | Xi Pardee <xi.pardee@intel.com> | 2024-04-26 03:27:51 +0300 |
---|---|---|
committer | Hans de Goede <hdegoede@redhat.com> | 2024-04-29 14:18:20 +0300 |
commit | d8dc1b95dec9586dacfc3963c94b3f89c8a95a2b (patch) | |
tree | 161718ca7e637bf1882ad4ff595a5376e45e5b55 /drivers/platform/x86/intel | |
parent | 4f3eec14729eced6ef5ef7242b63ca14377d87fe (diff) | |
download | linux-d8dc1b95dec9586dacfc3963c94b3f89c8a95a2b.tar.xz |
platform/x86:intel/pmc: Add support to show S0ix blocker counter
S0ix blocker counter is available in PWRM space. Add support to
read and show S0ix blocker counter value through debugfs.
Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20240426002752.2504282-3-xi.pardee@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel')
-rw-r--r-- | drivers/platform/x86/intel/pmc/core.c | 38 | ||||
-rw-r--r-- | drivers/platform/x86/intel/pmc/core.h | 6 |
2 files changed, 44 insertions, 0 deletions
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 10c96c1a850a..2ad2f8753e5d 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -678,6 +678,41 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); +static int pmc_core_s0ix_blocker_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + unsigned int pmcidx; + + for (pmcidx = 0; pmcidx < ARRAY_SIZE(pmcdev->pmcs); pmcidx++) { + const struct pmc_bit_map **maps; + unsigned int arr_size, r_idx; + u32 offset, counter; + struct pmc *pmc; + + pmc = pmcdev->pmcs[pmcidx]; + if (!pmc) + continue; + maps = pmc->map->s0ix_blocker_maps; + offset = pmc->map->s0ix_blocker_offset; + arr_size = pmc_core_lpm_get_arr_size(maps); + + for (r_idx = 0; r_idx < arr_size; r_idx++) { + const struct pmc_bit_map *map; + + for (map = maps[r_idx]; map->name; map++) { + if (!map->blk) + continue; + counter = pmc_core_reg_read(pmc, offset); + seq_printf(s, "PMC%d:%-30s %-30d\n", pmcidx, + map->name, counter); + offset += map->blk * S0IX_BLK_SIZE; + } + } + } + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_s0ix_blocker); + static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset, const int lpm_adj_x2) { @@ -1197,6 +1232,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops); + if (primary_pmc->map->s0ix_blocker_maps) + debugfs_create_file("s0ix_blocker", 0444, dir, pmcdev, &pmc_core_s0ix_blocker_fops); + debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc, &pmc_core_pkgc_fops); diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 18ba4f901c10..88acfa801b5a 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -22,6 +22,7 @@ struct telem_endpoint; #define PMC_BASE_ADDR_DEFAULT 0xFE000000 #define MAX_NUM_PMC 3 +#define S0IX_BLK_SIZE 4 /* Sunrise Point Power Management Controller PCI Device ID */ #define SPT_PMC_PCI_DEVICE_ID 0x9d21 @@ -288,6 +289,7 @@ extern const char *pmc_lpm_modes[]; struct pmc_bit_map { const char *name; u32 bit_mask; + u8 blk; }; /** @@ -298,6 +300,7 @@ struct pmc_bit_map { * @pll_sts: Maps name of PLL to corresponding bit status * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets + * @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit * @regmap_length: Length of memory to map from PWRMBASE address to access @@ -307,6 +310,7 @@ struct pmc_bit_map { * @pm_cfg_offset: PWRMBASE offset to PM_CFG register * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* + * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter * * Each PCH has unique set of register offsets and bit indexes. This structure * captures them to have a common implementation. @@ -319,6 +323,7 @@ struct pmc_reg_map { const struct pmc_bit_map *ltr_show_sts; const struct pmc_bit_map *msr_sts; const struct pmc_bit_map **lpm_sts; + const struct pmc_bit_map **s0ix_blocker_maps; const u32 slp_s0_offset; const int slp_s0_res_counter_step; const u32 ltr_ignore_offset; @@ -330,6 +335,7 @@ struct pmc_reg_map { const u32 slps0_dbg_offset; const u32 ltr_ignore_max; const u32 pm_vric1_offset; + const u32 s0ix_blocker_offset; /* Low Power Mode registers */ const int lpm_num_maps; const int lpm_num_modes; |