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| author | Vadim Pasternak <vadimp@nvidia.com> | 2023-02-08 09:33:28 +0300 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2023-02-13 14:07:50 +0300 |
| commit | cefdbc7815660be4d0f2d290860dcfb0f9d285e4 (patch) | |
| tree | c5099163cba4f03658a934dcfa76e566aa7074b4 /drivers/platform | |
| parent | 26917eab144c8515435ef9175fdd5dddf9f0f000 (diff) | |
| download | linux-cefdbc7815660be4d0f2d290860dcfb0f9d285e4.tar.xz | |
platform: mellanox: mlx-platform: Add mux selection register to regmap
Extend writeable, readable, volatile registers of the 'regmap' object
with for I2C mux selector registers.
The motivation is to pass this object extended with selector registers
to I2C mux driver working over ‘regmap’.
Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20230208063331.15560-12-vadimp@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/x86/mlx-platform.c | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index e541046c9100..60062d9f3b9b 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -139,6 +139,10 @@ #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 #define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 +#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb +#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda +#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc +#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 @@ -172,23 +176,19 @@ #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 -#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb -#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda -#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc -#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ - MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ + MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ MLXPLAT_CPLD_LPC_PIO_OFFSET) #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ - MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ + MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ MLXPLAT_CPLD_LPC_PIO_OFFSET) #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ - MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ + MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ MLXPLAT_CPLD_LPC_PIO_OFFSET) #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ - MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ + MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ MLXPLAT_CPLD_LPC_PIO_OFFSET) /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ @@ -4980,6 +4980,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: @@ -5107,6 +5111,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: @@ -5254,6 +5262,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: |