diff options
author | Min Li <min.li.xe@renesas.com> | 2021-09-13 23:12:33 +0300 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2021-09-14 16:22:12 +0300 |
commit | 794c3dffacc166f7a8f7a555ff7e75fcdb644a51 (patch) | |
tree | 5eff892416d83f49305db8756c22e3ecd355b89f /drivers/ptp/ptp_clockmatrix.h | |
parent | c70aae139d3940a0ae0922ed52384e14f092a963 (diff) | |
download | linux-794c3dffacc166f7a8f7a555ff7e75fcdb644a51.tar.xz |
ptp: ptp_clockmatrix: Add support for FW 5.2 (8A34005)
So far we don't need to support new 5.2 functions but different register
addresses
Signed-off-by: Min Li <min.li.xe@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_clockmatrix.h')
-rw-r--r-- | drivers/ptp/ptp_clockmatrix.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index fb323271063e..843a9d7129c5 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -57,10 +57,10 @@ #define IDTCM_MAX_WRITE_COUNT (512) -#define FULL_FW_CFG_BYTES (SCRATCH - GPIO_USER_CONTROL) -#define FULL_FW_CFG_SKIPPED_BYTES (((SCRATCH >> 7) \ - - (GPIO_USER_CONTROL >> 7)) \ - * 4) /* 4 bytes skipped every 0x80 */ +/* + * Return register address based on passed in firmware version + */ +#define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) /* Values of DPLL_N.DPLL_MODE.PLL_MODE */ enum pll_mode { @@ -119,6 +119,12 @@ enum dpll_state { DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP, }; +enum fw_version { + V_DEFAULT = 0, + V487 = 1, + V520 = 2, +}; + struct idtcm; struct idtcm_channel { @@ -134,6 +140,7 @@ struct idtcm_channel { u16 tod_write; u16 tod_n; u16 hw_dpll_n; + u8 sync_src; enum pll_mode pll_mode; u8 pll; u16 output_mask; @@ -145,7 +152,7 @@ struct idtcm { u8 page_offset; u8 tod_mask; char version[16]; - u8 deprecated; + enum fw_version fw_ver; /* Overhead calculation for adjtime */ u8 calculate_overhead_flag; |