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authorVincent Cheng <vincent.cheng.xh@renesas.com>2021-02-17 08:42:12 +0300
committerDavid S. Miller <davem@davemloft.net>2021-02-18 00:49:25 +0300
commit797d3186544fcd5bfd7a03b9ef3e20c1db3802b8 (patch)
treee6e42ecdfd4a9c36826d3d68b201f081be2cfce4 /drivers/ptp/ptp_clockmatrix.h
parent857490807368026116a16306ab89e9b71cad60ab (diff)
downloadlinux-797d3186544fcd5bfd7a03b9ef3e20c1db3802b8.tar.xz
ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not locked, then the alignment will fail and there will be a fixed offset between the internal 1 PPS clock and the output clock. After loading the device firmware, poll the system APLL and DPLL for locked state prior to initialization, timing out after 2 seconds. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_clockmatrix.h')
-rw-r--r--drivers/ptp/ptp_clockmatrix.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 645de2c66b64..023323680db7 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -51,6 +51,9 @@
#define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
#define TOD_BYTE_COUNT (11)
+#define LOCK_TIMEOUT_MS (2000)
+#define LOCK_POLL_INTERVAL_MS (10)
+
#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
#define IDTCM_MAX_WRITE_COUNT (512)
@@ -105,6 +108,18 @@ enum scsr_tod_write_type_sel {
SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
};
+/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */
+enum dpll_state {
+ DPLL_STATE_MIN = 0,
+ DPLL_STATE_FREERUN = DPLL_STATE_MIN,
+ DPLL_STATE_LOCKACQ = 1,
+ DPLL_STATE_LOCKREC = 2,
+ DPLL_STATE_LOCKED = 3,
+ DPLL_STATE_HOLDOVER = 4,
+ DPLL_STATE_OPEN_LOOP = 5,
+ DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,
+};
+
struct idtcm;
struct idtcm_channel {