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authorConor Dooley <conor.dooley@microchip.com>2022-09-09 15:31:14 +0300
committerClaudiu Beznea <claudiu.beznea@microchip.com>2022-09-14 10:55:17 +0300
commit05f9e36370c1517c8e03325f38910fd7ad30b177 (patch)
tree6c6cd9ece38ac2269ea65b12d851086c569a0fc1 /drivers/reset/Kconfig
parentb56bae2dd6fda6baf3bb74af3812676eebdd52f2 (diff)
downloadlinux-05f9e36370c1517c8e03325f38910fd7ad30b177.tar.xz
reset: add polarfire soc reset support
Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
Diffstat (limited to 'drivers/reset/Kconfig')
-rw-r--r--drivers/reset/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 806773e88832..85f7abde3766 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -152,6 +152,13 @@ config RESET_PISTACHIO
help
This enables the reset driver for ImgTec Pistachio SoCs.
+config RESET_POLARFIRE_SOC
+ bool "Microchip PolarFire SoC (MPFS) Reset Driver"
+ depends on AUXILIARY_BUS && MCHP_CLK_MPFS
+ default MCHP_CLK_MPFS
+ help
+ This driver supports peripheral reset for the Microchip PolarFire SoC
+
config RESET_QCOM_AOSS
tristate "Qcom AOSS Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST