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authorJoel Stanley <joel@jms.id.au>2018-02-20 04:43:29 +0300
committerPhilipp Zabel <p.zabel@pengutronix.de>2018-02-20 19:42:29 +0300
commit1d7592f84f92c6344978186fdbe547af044274b5 (patch)
treec185c0f0b87fbe999c5bd9ccf52c28450a3bd3bb /drivers/reset/Kconfig
parent14b5057a2f84b9da246e5bda29c9fd914a8f691c (diff)
downloadlinux-1d7592f84f92c6344978186fdbe547af044274b5.tar.xz
reset: simple: Enable for ASPEED systems
ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/reset/Kconfig')
-rw-r--r--drivers/reset/Kconfig10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 7fc77696bb1e..18f152d251d7 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -83,14 +83,18 @@ config RESET_PISTACHIO
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
- default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
+ default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
- Currently this driver supports Altera SoCFPGAs, the RCC reset
- controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family.
+ Currently this driver supports:
+ - Altera SoCFPGAs
+ - ASPEED BMC SoCs
+ - RCC reset controller in STM32 MCUs
+ - Allwinner SoCs
+ - ZTE's zx2967 family
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI