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authorJohn Garry <john.garry@huawei.com>2015-11-17 19:50:34 +0300
committerMartin K. Petersen <martin.petersen@oracle.com>2015-11-26 06:12:53 +0300
commit6be6de18891d5533451b2c00424f6a557dc901ec (patch)
tree33f75b9e54c23e3215962706b24456d6029ca5cf /drivers/scsi/hisi_sas/hisi_sas.h
parentc799d6bd8fe4a82333fd11f8699f621e10af2f4b (diff)
downloadlinux-6be6de18891d5533451b2c00424f6a557dc901ec.tar.xz
hisi_sas: Allocate memories and create pools
Allocate DMA and non-DMA memories for the controller. Also create DMA pools. These include: - Delivery queues - Completion queues - Command status buffer - Command table - ITCT (For device context) - Host slot info - IO status - Breakpoint - host slot indexing - SG data - FIS - interrupts names Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/hisi_sas/hisi_sas.h')
-rw-r--r--drivers/scsi/hisi_sas/hisi_sas.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 19d40b76508f..6d1b7d88cb38 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -24,10 +24,17 @@
#define DRV_VERSION "v1.0"
#define HISI_SAS_MAX_PHYS 9
+#define HISI_SAS_MAX_QUEUES 32
+#define HISI_SAS_QUEUE_SLOTS 512
#define HISI_SAS_MAX_ITCT_ENTRIES 4096
#define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
#define HISI_SAS_COMMAND_ENTRIES 8192
+#define HISI_SAS_STATUS_BUF_SZ \
+ (sizeof(struct hisi_sas_err_record) + 1024)
+#define HISI_SAS_COMMAND_TABLE_SZ \
+ (((sizeof(union hisi_sas_command_table)+3)/4)*4)
+
#define HISI_SAS_NAME_LEN 32
struct hisi_sas_phy {
@@ -38,7 +45,11 @@ struct hisi_sas_port {
struct asd_sas_port sas_port;
};
+struct hisi_sas_slot {
+};
+
struct hisi_sas_hw {
+ int complete_hdr_size;
};
struct hisi_hba {
@@ -63,6 +74,25 @@ struct hisi_hba {
int queue_count;
char *int_names;
+
+ struct dma_pool *sge_page_pool;
+ struct dma_pool *command_table_pool;
+ struct dma_pool *status_buffer_pool;
+ struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
+ dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
+ void *complete_hdr[HISI_SAS_MAX_QUEUES];
+ dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
+ struct hisi_sas_initial_fis *initial_fis;
+ dma_addr_t initial_fis_dma;
+ struct hisi_sas_itct *itct;
+ dma_addr_t itct_dma;
+ struct hisi_sas_iost *iost;
+ dma_addr_t iost_dma;
+ struct hisi_sas_breakpoint *breakpoint;
+ dma_addr_t breakpoint_dma;
+ struct hisi_sas_breakpoint *sata_breakpoint;
+ dma_addr_t sata_breakpoint_dma;
+ struct hisi_sas_slot *slot_info;
const struct hisi_sas_hw *hw; /* Low level hw interface */
};