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authorZong Li <zong.li@sifive.com>2022-09-13 09:18:16 +0300
committerPalmer Dabbelt <palmer@rivosinc.com>2022-10-13 21:06:55 +0300
commitafc7a5834f0de13aee46df62f09e479c1bbf7b9d (patch)
tree59545e740c8bd6e4d0077132ec8f178164f9a10b /drivers/soc
parent696ab9bda22a770d079dc3a23bac9aaa553d98f4 (diff)
downloadlinux-afc7a5834f0de13aee46df62f09e479c1bbf7b9d.tar.xz
soc: sifive: ccache: define the macro for the register shifts
Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/sifive/sifive_ccache.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 91f0c2b32ea2..1c171150e878 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -13,6 +13,7 @@
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/device.h>
+#include <linux/bitfield.h>
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_ccache.h>
@@ -33,6 +34,11 @@
#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
#define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
+#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
+#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
+#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
+
#define SIFIVE_CCACHE_WAYENABLE 0x08
#define SIFIVE_CCACHE_ECCINJECTERR 0x40
@@ -87,11 +93,11 @@ static void ccache_config_read(void)
u32 cfg;
cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-
- pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
- (cfg & 0xff), (cfg >> 8) & 0xff,
- BIT_ULL((cfg >> 16) & 0xff),
- BIT_ULL((cfg >> 24) & 0xff));
+ pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
+ FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
+ FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
+ BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
+ BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
pr_info("Index of the largest way enabled: %u\n", cfg);