Merge tag 'spi-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "One small core feature this time around but mostly driver improvements
  and additions for SPI:

   - Add support for controlling the idle state of MOSI, some systems
     can support this and depending on the system integration may need
     it to avoid glitching in some situations

   - Support for polling mode in the S3C64xx driver and DMA on the
     Qualcomm QSPI driver

   - Support for several Allwinner SoCs, AMD Pensando Elba, Intel Mount
     Evans, Renesas RZ/V2M, and ST STM32H7"

* tag 'spi-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits)
  spi: dt-bindings: atmel,at91rm9200-spi: fix broken sam9x7 compatible
  spi: dt-bindings: atmel,at91rm9200-spi: add sam9x7 compatible
  spi: Add support for Renesas CSI
  spi: dt-bindings: Add bindings for RZ/V2M CSI
  spi: sun6i: Use the new helper to derive the xfer timeout value
  spi: atmel: Prevent false timeouts on long transfers
  spi: dt-bindings: stm32: do not disable spi-slave property for stm32f4-f7
  spi: Create a helper to derive adaptive timeouts
  spi: spi-geni-qcom: correctly handle -EPROBE_DEFER from dma_request_chan()
  spi: stm32: disable spi-slave property for stm32f4-f7
  spi: stm32: introduction of stm32h7 SPI device mode support
  spi: stm32: use dmaengine_terminate_{a}sync instead of _all
  spi: stm32: renaming of spi_master into spi_controller
  spi: dw: Remove misleading comment for Mount Evans SoC
  spi: dt-bindings: snps,dw-apb-ssi: Add compatible for Intel Mount Evans SoC
  spi: dw: Add compatible for Intel Mount Evans SoC
  spi: s3c64xx: Use dev_err_probe()
  spi: s3c64xx: Use the managed spi master allocation function
  spi: spl022: Probe defer is no error
  spi: spi-imx: fix mixing of native and gpio chipselects for imx51/imx53/imx6 variants
  ...

1 files changed, 19 insertions, 0 deletions

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 32449bef4415..abf10f92415d 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -40,6 +40,7 @@
 #define CQSPI_SUPPORT_EXTERNAL_DMA	BIT(2)
 #define CQSPI_NO_SUPPORT_WR_COMPLETION	BIT(3)
 #define CQSPI_SLOW_SRAM		BIT(4)
+#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR	BIT(5)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
@@ -90,6 +91,7 @@ struct cqspi_st {
 	u32			pd_dev_id;
 	bool			wr_completion;
 	bool			slow_sram;
+	bool			apb_ahb_hazard;
 };
 
 struct cqspi_driver_platdata {
@@ -1027,6 +1029,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 	if (cqspi->wr_delay)
 		ndelay(cqspi->wr_delay);
 
+	/*
+	 * If a hazard exists between the APB and AHB interfaces, perform a
+	 * dummy readback from the controller to ensure synchronization.
+	 */
+	if (cqspi->apb_ahb_hazard)
+		readl(reg_base + CQSPI_REG_INDIRECTWR);
+
 	while (remaining > 0) {
 		size_t write_words, mod_bytes;
 
@@ -1754,6 +1763,8 @@ static int cqspi_probe(struct platform_device *pdev)
 			cqspi->wr_completion = false;
 		if (ddata->quirks & CQSPI_SLOW_SRAM)
 			cqspi->slow_sram = true;
+		if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
+			cqspi->apb_ahb_hazard = true;
 
 		if (of_device_is_compatible(pdev->dev.of_node,
 					    "xlnx,versal-ospi-1.0")) {
@@ -1888,6 +1899,10 @@ static const struct cqspi_driver_platdata jh7110_qspi = {
 	.quirks = CQSPI_DISABLE_DAC_MODE,
 };
 
+static const struct cqspi_driver_platdata pensando_cdns_qspi = {
+	.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
 	{
 		.compatible = "cdns,qspi-nor",
@@ -1917,6 +1932,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
 		.compatible = "starfive,jh7110-qspi",
 		.data = &jh7110_qspi,
 	},
+	{
+		.compatible = "amd,pensando-elba-qspi",
+		.data = &pensando_cdns_qspi,
+	},
 	{ /* end of table */ }
 };