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authorTim Harvey <tharvey@gateworks.com>2020-05-28 18:46:39 +0300
committerMark Brown <broonie@kernel.org>2020-06-16 02:38:39 +0300
commite8510d43f219beff1f426080049a5462148afd2f (patch)
tree362e8473113d24f6ae5fa01ab349c76ef0265b26 /drivers/spi/spi-cavium-thunderx.c
parenteb8d6d464a27850498dced21a8450e85d4a02009 (diff)
downloadlinux-e8510d43f219beff1f426080049a5462148afd2f.tar.xz
spi: spi-cavium-thunderx: flag controller as half duplex
The OcteonTX (TX1/ThunderX) SPI controller does not support full duplex transactions. Set the appropriate flag such that the spi core will return -EINVAL on such transactions requested by chip drivers. This is an RFC as I need someone from Marvell/Cavium to confirm if this driver is used for other silicon that does support full duplex transfers (in which case we will need to identify that we are running on the ThunderX arch before setting the flag). Signed-off-by: Tim Harvey <tharvey@gateworks.com> Cc: Robert Richter <rrichter@marvell.com> Link: https://lore.kernel.org/r/1590680799-5640-1-git-send-email-tharvey@gateworks.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-cavium-thunderx.c')
-rw-r--r--drivers/spi/spi-cavium-thunderx.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-cavium-thunderx.c b/drivers/spi/spi-cavium-thunderx.c
index fd6b9caffaf0..60c0d6934654 100644
--- a/drivers/spi/spi-cavium-thunderx.c
+++ b/drivers/spi/spi-cavium-thunderx.c
@@ -64,6 +64,7 @@ static int thunderx_spi_probe(struct pci_dev *pdev,
p->sys_freq = SYS_FREQ_DEFAULT;
dev_info(dev, "Set system clock to %u\n", p->sys_freq);
+ master->flags = SPI_MASTER_HALF_DUPLEX;
master->num_chipselect = 4;
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
SPI_LSB_FIRST | SPI_3WIRE;