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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2020-09-20 14:28:54 +0300
committerMark Brown <broonie@kernel.org>2020-09-29 19:22:27 +0300
commitffb7ca54c95b4c76ad8a9aa1b2b16d61df2a7139 (patch)
tree6073dbb8a4893e4fb6de9a6c1fd3625660d30d47 /drivers/spi/spi-dw.h
parentcc760f3143f53ea8387cd76cffc43bdc89db9df4 (diff)
downloadlinux-ffb7ca54c95b4c76ad8a9aa1b2b16d61df2a7139.tar.xz
spi: dw: Add KeemBay Master capability
In a further commit we'll have to get rid of the update_cr0() callback and define a DW SSI capability instead. Since Keem Bay master/slave functionality is controller by the CTRL0 register bitfield, we need to first move the master mode selection into the internal corresponding update_cr0 method, which would be activated by means of the dedicated DW_SPI_CAP_KEEMBAY_MST capability setup. Note this will be also useful if the driver will be ever altered to support the DW SPI slave interface. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20200920112914.26501-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-dw.h')
-rw-r--r--drivers/spi/spi-dw.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index b11fc873c3a7..56be1ad2ac0e 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -71,6 +71,13 @@
#define DWC_SSI_CTRLR0_FRF_OFFSET 6
#define DWC_SSI_CTRLR0_DFS_OFFSET 0
+/*
+ * For Keem Bay, CTRLR0[31] is used to select controller mode.
+ * 0: SSI is slave
+ * 1: SSI is master
+ */
+#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
+
/* Bit fields in SR, 7 bits */
#define SR_MASK 0x7f /* cover 7 bits */
#define SR_BUSY (1 << 0)
@@ -101,6 +108,7 @@ enum dw_ssi_type {
/* DW SPI capabilities */
#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
+#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
struct dw_spi;
struct dw_spi_dma_ops {