staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core

This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.

See Xilinx PG080 document for IP details.

https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

The driver currently supports only store-forward mode with a 32-bit
AXI4 Lite interface. DOES NOT support:
        - cut-through mode
        - AXI4 (non-lite)

Signed-off-by: Jacob Feder <jacobsfeder@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/staging/axis-fifo/Makefile b/drivers/staging/axis-fifo/Makefile
new file mode 100644
index 000000000000..fe62cd1ac5de
--- /dev/null
+++ b/drivers/staging/axis-fifo/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo.o