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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-09-01 16:36:35 +0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2017-09-23 22:03:53 +0300 |
| commit | 90154e130f45f4fcad595058cc2d34ce412bec33 (patch) | |
| tree | a8ef3b86a1b20e38461c67d186c5b4efb337ce9b /drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c | |
| parent | 5fc90b632ea9a107ed6b71eb7058bb58e1b5493b (diff) | |
| download | linux-90154e130f45f4fcad595058cc2d34ce412bec33.tar.xz | |
media: staging: atomisp: Don't override D3 delay settings here
The d3_delay parameter is set by arch/x86/pci/intel_mid_pci.c and
drivers/pci/quirks.c.
No need to override that settings in unrelated driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c')
| -rw-r--r-- | drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c b/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c index 0d01a269989d..341bfd3ab313 100644 --- a/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c +++ b/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c @@ -161,36 +161,3 @@ u32 intel_mid_soc_stepping(void) return pci_root->revision; } EXPORT_SYMBOL(intel_mid_soc_stepping); - -static bool is_south_complex_device(struct pci_dev *dev) -{ - unsigned int base_class = dev->class >> 16; - unsigned int sub_class = (dev->class & SUB_CLASS_MASK) >> 8; - - /* other than camera, pci bridges and display, - * everything else are south complex devices. - */ - if (((base_class == PCI_BASE_CLASS_MULTIMEDIA) && - (sub_class == ISP_SUB_CLASS)) || - (base_class == PCI_BASE_CLASS_BRIDGE) || - ((base_class == PCI_BASE_CLASS_DISPLAY) && !sub_class)) - return false; - else - return true; -} - -/* In BYT platform, d3_delay for internal south complex devices, - * they are not subject to 10 ms d3 to d0 delay required by pci spec. - */ -static void pci_d3_delay_fixup(struct pci_dev *dev) -{ - if (platform_is(INTEL_ATOM_BYT) || - platform_is(INTEL_ATOM_CHT)) { - /* All internal devices are in bus 0. */ - if (dev->bus->number == 0 && is_south_complex_device(dev)) { - dev->d3_delay = INTERNAL_PCI_PM_D3_WAIT; - dev->d3cold_delay = INTERNAL_PCI_PM_D3_WAIT; - } - } -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3_delay_fixup); |