diff options
| author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2013-08-28 19:03:50 +0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2013-12-11 12:53:31 +0400 |
| commit | ade1ec3736c432981fefaa07b20e818c8501a44e (patch) | |
| tree | 8edf0be276f13c33aa3275bdc3df288115958ca6 /drivers/staging/media/omap4iss/iss_regs.h | |
| parent | 29ee62616348d7c7680728ad7df8d52fa5e67c0c (diff) | |
| download | linux-ade1ec3736c432981fefaa07b20e818c8501a44e.tar.xz | |
[media] v4l: omap4iss: Define more ISS and ISP IRQ register bits
Add more register definitions at iss_regs.h and improve some register
names.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'drivers/staging/media/omap4iss/iss_regs.h')
| -rw-r--r-- | drivers/staging/media/omap4iss/iss_regs.h | 36 |
1 files changed, 27 insertions, 9 deletions
diff --git a/drivers/staging/media/omap4iss/iss_regs.h b/drivers/staging/media/omap4iss/iss_regs.h index 7327d0c1ae37..16975ca44246 100644 --- a/drivers/staging/media/omap4iss/iss_regs.h +++ b/drivers/staging/media/omap4iss/iss_regs.h @@ -24,12 +24,16 @@ #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE 0x2 #define ISS_HL_SYSCONFIG_SOFTRESET (1 << 0) -#define ISS_HL_IRQSTATUS_5 (0x24 + (0x10 * 5)) -#define ISS_HL_IRQENABLE_5_SET (0x28 + (0x10 * 5)) -#define ISS_HL_IRQENABLE_5_CLR (0x2C + (0x10 * 5)) +#define ISS_HL_IRQSTATUS_RAW(i) (0x20 + (0x10 * (i))) +#define ISS_HL_IRQSTATUS(i) (0x24 + (0x10 * (i))) +#define ISS_HL_IRQENABLE_SET(i) (0x28 + (0x10 * (i))) +#define ISS_HL_IRQENABLE_CLR(i) (0x2c + (0x10 * (i))) +#define ISS_HL_IRQ_HS_VS (1 << 17) +#define ISS_HL_IRQ_SIMCOP(i) (1 << (12 + (i))) #define ISS_HL_IRQ_BTE (1 << 11) #define ISS_HL_IRQ_CBUFF (1 << 10) +#define ISS_HL_IRQ_CCP2(i) (1 << ((i) > 3 ? 16 : 14 + (i))) #define ISS_HL_IRQ_CSIB (1 << 5) #define ISS_HL_IRQ_CSIA (1 << 4) #define ISS_HL_IRQ_ISP(i) (1 << (i)) @@ -267,16 +271,30 @@ /* Bits shared for ISP5_IRQ* registers */ #define ISP5_IRQ_OCP_ERR (1 << 31) +#define ISP5_IRQ_IPIPE_INT_DPC_RNEW1 (1 << 29) +#define ISP5_IRQ_IPIPE_INT_DPC_RNEW0 (1 << 28) +#define ISP5_IRQ_IPIPE_INT_DPC_INIT (1 << 27) +#define ISP5_IRQ_IPIPE_INT_EOF (1 << 25) +#define ISP5_IRQ_H3A_INT_EOF (1 << 24) +#define ISP5_IRQ_RSZ_INT_EOF1 (1 << 23) #define ISP5_IRQ_RSZ_INT_EOF0 (1 << 22) -#define ISP5_IRQ_RSZ_FIFO_IN_BLK (1 << 19) +#define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR (1 << 19) #define ISP5_IRQ_RSZ_FIFO_OVF (1 << 18) +#define ISP5_IRQ_RSZ_INT_CYC_RSZB (1 << 17) #define ISP5_IRQ_RSZ_INT_CYC_RSZA (1 << 16) #define ISP5_IRQ_RSZ_INT_DMA (1 << 15) -#define ISP5_IRQ_IPIPEIF (1 << 9) -#define ISP5_IRQ_ISIF3 (1 << 3) -#define ISP5_IRQ_ISIF2 (1 << 2) -#define ISP5_IRQ_ISIF1 (1 << 1) -#define ISP5_IRQ_ISIF0 (1 << 0) +#define ISP5_IRQ_RSZ_INT_LAST_PIX (1 << 14) +#define ISP5_IRQ_RSZ_INT_REG (1 << 13) +#define ISP5_IRQ_H3A_INT (1 << 12) +#define ISP5_IRQ_AF_INT (1 << 11) +#define ISP5_IRQ_AEW_INT (1 << 10) +#define ISP5_IRQ_IPIPEIF_IRQ (1 << 9) +#define ISP5_IRQ_IPIPE_INT_HST (1 << 8) +#define ISP5_IRQ_IPIPE_INT_BSC (1 << 7) +#define ISP5_IRQ_IPIPE_INT_DMA (1 << 6) +#define ISP5_IRQ_IPIPE_INT_LAST_PIX (1 << 5) +#define ISP5_IRQ_IPIPE_INT_REG (1 << 4) +#define ISP5_IRQ_ISIF_INT(i) (1 << (i)) #define ISP5_CTRL (0x006C) #define ISP5_CTRL_MSTANDBY (1 << 24) |