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authorJonathan Bergh <bergh.jonathan@gmail.com>2024-03-03 13:05:46 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2024-03-05 17:13:30 +0300
commit9bed49bfd17c8ffa808c250244ea9adf0497dfd6 (patch)
tree8220f6664ae92084f1a1447c68130bb16f398307 /drivers/staging
parent7485b3e350c801f5105cc40ee7c1d871e79a47dc (diff)
downloadlinux-9bed49bfd17c8ffa808c250244ea9adf0497dfd6.tar.xz
staging: vme_user: Fix misaligned closing comment */
This patch makes the following change: * Ensures the trailing */ for comments is on the same line as the opening /* Signed-off-by: Jonathan Bergh <bergh.jonathan@gmail.com> Link: https://lore.kernel.org/r/20240303100547.153636-1-bergh.jonathan@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/vme_user/vme_tsi148.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/staging/vme_user/vme_tsi148.h b/drivers/staging/vme_user/vme_tsi148.h
index 4dd224d0b86e..db246cbc54c3 100644
--- a/drivers/staging/vme_user/vme_tsi148.h
+++ b/drivers/staging/vme_user/vme_tsi148.h
@@ -691,8 +691,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VMCTRL_RMWEN BIT(20) /* RMW Enable */
-#define TSI148_LCSR_VMCTRL_ATO_M (7 << 16) /* Master Access Time-out Mask
- */
+#define TSI148_LCSR_VMCTRL_ATO_M (7 << 16) /* Master Access Time-out Mask */
#define TSI148_LCSR_VMCTRL_ATO_32 (0 << 16) /* 32 us */
#define TSI148_LCSR_VMCTRL_ATO_128 BIT(16) /* 128 us */
#define TSI148_LCSR_VMCTRL_ATO_512 (2 << 16) /* 512 us */
@@ -753,8 +752,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VCTRL_DLT_16384 (0xB << 24) /* 16384 VCLKS */
#define TSI148_LCSR_VCTRL_DLT_32768 (0xC << 24) /* 32768 VCLKS */
-#define TSI148_LCSR_VCTRL_NERBB BIT(20) /* No Early Release of Bus Busy
- */
+#define TSI148_LCSR_VCTRL_NERBB BIT(20) /* No Early Release of Bus Busy */
#define TSI148_LCSR_VCTRL_SRESET BIT(17) /* System Reset */
#define TSI148_LCSR_VCTRL_LRESET BIT(16) /* Local Reset */