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authorNicolas Pitre <npitre@baylibre.com>2024-04-02 06:25:44 +0300
committerDaniel Lezcano <daniel.lezcano@linaro.org>2024-04-23 13:40:30 +0300
commit684cbb49f9ceed6be0f33dac9d62089e7cd1c032 (patch)
treed437d1d56f08ba6ae484be530dd390912048f783 /drivers/thermal/mediatek
parenta4c1ab2f4c6c94edfc6481edf37e141079e24f1d (diff)
downloadlinux-684cbb49f9ceed6be0f33dac9d62089e7cd1c032.tar.xz
thermal/drivers/mediatek/lvts_thermal: Provision for gt variable location
The golden temperature calibration value in nvram is not always the 3rd byte. A future commit will prove this assumption wrong. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240402032729.2736685-11-nico@fluxnic.net
Diffstat (limited to 'drivers/thermal/mediatek')
-rw-r--r--drivers/thermal/mediatek/lvts_thermal.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 6f711aec0d0f..34f5a8150430 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -116,6 +116,7 @@ struct lvts_data {
int num_lvts_ctrl;
int temp_factor;
int temp_offset;
+ int gt_calib_bit_offset;
};
struct lvts_sensor {
@@ -745,20 +746,21 @@ static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td
return 0;
}
-static int lvts_golden_temp_init(struct device *dev, u8 *calib, int temp_offset)
+static int lvts_golden_temp_init(struct device *dev, u8 *calib,
+ const struct lvts_data *lvts_data)
{
u32 gt;
/*
- * The golden temp information is contained in the 4th byte (index = 3)
- * of efuse data.
+ * The golden temp information is contained in the first 32-bit
+ * word of efuse data at a specific bit offset.
*/
- gt = calib[3];
+ gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff;
if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
golden_temp = gt;
- golden_temp_offset = golden_temp * 500 + temp_offset;
+ golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset;
return 0;
}
@@ -777,7 +779,7 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
if (ret)
return ret;
- ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data->temp_offset);
+ ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data);
if (ret)
return ret;
@@ -1600,6 +1602,7 @@ static const struct lvts_data mt7988_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT7988,
.temp_offset = LVTS_COEFF_B_MT7988,
+ .gt_calib_bit_offset = 24,
};
static const struct lvts_data mt8186_lvts_data = {
@@ -1607,6 +1610,7 @@ static const struct lvts_data mt8186_lvts_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT7988,
.temp_offset = LVTS_COEFF_B_MT7988,
+ .gt_calib_bit_offset = 24,
};
static const struct lvts_data mt8192_lvts_mcu_data = {
@@ -1614,6 +1618,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT8195,
.temp_offset = LVTS_COEFF_B_MT8195,
+ .gt_calib_bit_offset = 24,
};
static const struct lvts_data mt8192_lvts_ap_data = {
@@ -1621,6 +1626,7 @@ static const struct lvts_data mt8192_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT8195,
.temp_offset = LVTS_COEFF_B_MT8195,
+ .gt_calib_bit_offset = 24,
};
static const struct lvts_data mt8195_lvts_mcu_data = {
@@ -1628,6 +1634,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT8195,
.temp_offset = LVTS_COEFF_B_MT8195,
+ .gt_calib_bit_offset = 24,
};
static const struct lvts_data mt8195_lvts_ap_data = {
@@ -1635,6 +1642,7 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
.temp_factor = LVTS_COEFF_A_MT8195,
.temp_offset = LVTS_COEFF_B_MT8195,
+ .gt_calib_bit_offset = 24,
};
static const struct of_device_id lvts_of_match[] = {