diff options
| author | Sevak Arakelyan <sevaka@synopsys.com> | 2018-01-24 16:41:48 +0300 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-03-13 11:47:47 +0300 |
| commit | 6f80b6de0ecf65077b53c86967c714d42f4299e0 (patch) | |
| tree | 05f46180122561844154729d607cf997cd627445 /drivers/usb/dwc2/core.h | |
| parent | 391f8081d20bf1fcffc5556f94f3cf75c4d14e01 (diff) | |
| download | linux-6f80b6de0ecf65077b53c86967c714d42f4299e0.tar.xz | |
usb: dwc2: Add core parameters for LPM support
Add lpm, lpm_clock_gating, besl, hird_threshold_en and hird_threshold
core parameters. These will indicate LPM and LPM Errata support
as well as chosen L1 sleeping mode for the core and PHY.
Signed-off-by: Sevak Arakelyan <sevaka@synopsys.com>
Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc2/core.h')
| -rw-r--r-- | drivers/usb/dwc2/core.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index f6daa58446ae..bd6672b8c2ff 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -427,6 +427,19 @@ enum dwc2_ep0_state { * needed. * 0 - No (default) * 1 - Yes + * @lpm: Enable LPM support. + * 0 - No + * 1 - Yes + * @lpm_clock_gating: Enable core PHY clock gating. + * 0 - No + * 1 - Yes + * @besl: Enable LPM Errata support. + * 0 - No + * 1 - Yes + * @hird_threshold_en: HIRD or HIRD Threshold enable. + * 0 - No + * 1 - Yes + * @hird_threshold: Value of BESL or HIRD Threshold. * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO * register. * 0 - Deactivate the transceiver (default) @@ -486,6 +499,11 @@ struct dwc2_core_params { bool uframe_sched; bool external_id_pin_ctl; bool hibernation; + bool lpm; + bool lpm_clock_gating; + bool besl; + bool hird_threshold_en; + u8 hird_threshold; bool activate_stm_fs_transceiver; u16 max_packet_count; u32 max_transfer_size; @@ -595,6 +613,7 @@ struct dwc2_hw_params { unsigned total_fifo_size:16; unsigned power_optimized:1; unsigned utmi_phy_data_width:2; + unsigned lpm_mode:1; u32 snpsid; u32 dev_ep_dirs; u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; @@ -950,6 +969,7 @@ struct dwc2_hsotg { /* DWC OTG HW Release versions */ #define DWC2_CORE_REV_2_71a 0x4f54271a +#define DWC2_CORE_REV_2_80a 0x4f54280a #define DWC2_CORE_REV_2_90a 0x4f54290a #define DWC2_CORE_REV_2_91a 0x4f54291a #define DWC2_CORE_REV_2_92a 0x4f54292a |