summaryrefslogtreecommitdiff
path: root/drivers/usb/host/ehci-pci.c
diff options
context:
space:
mode:
authorRene Herman <rene.herman@gmail.com>2008-03-20 10:58:16 +0300
committerGreg Kroah-Hartman <gregkh@suse.de>2008-03-25 08:26:15 +0300
commit055b93c9e32a44acfe3e5e58b900f1e8fcd5f858 (patch)
treeb069544cd7a804c6a6d3be2b0d59b7356b8060e6 /drivers/usb/host/ehci-pci.c
parent7f170a632d67297b4076947f9b42f55f710ccd42 (diff)
downloadlinux-055b93c9e32a44acfe3e5e58b900f1e8fcd5f858.tar.xz
USB: ehci: stop vt6212 bus hogging
The VIA VT6212 defaults to only waiting 1us between passes over EHCI's async ring, which hammers PCI badly ... and by preventing other devices from accessing the bus, causes problems like drops in IDE throughput, a problem that's been bugging users of those chips for several years. A (partial) datasheet for this chip eventually turned up, letting us see how to make it use a VIA-specific register to switch over to the the normal 10us value instead, as suggested by the EHCI specification Solution noted by Lev A. Melnikovsky. It's not clear whether this register exists on other VIA chips; we know that it's ineffective on the vt8235. So this patch only applies to chips that seem to be incarnations of the (discrete) vt6212. Signed-off-by: Rene Herman <rene.herman@gmail.com> Tested-by: Lev A. Melnikovsky <melnikovsky@mail.ru> Tested-by: Alessandro Suardi <alessandro.suardi@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/host/ehci-pci.c')
-rw-r--r--drivers/usb/host/ehci-pci.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 3ba01664f821..72ccd56e36dd 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -152,6 +152,20 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
break;
}
break;
+ case PCI_VENDOR_ID_VIA:
+ if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
+ u8 tmp;
+
+ /* The VT6212 defaults to a 1 usec EHCI sleep time which
+ * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
+ * that sleep time use the conventional 10 usec.
+ */
+ pci_read_config_byte(pdev, 0x4b, &tmp);
+ if (tmp & 0x20)
+ break;
+ pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
+ }
+ break;
}
ehci_reset(ehci);