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authorMaxime Ripard <mripard@kernel.org>2024-01-29 16:20:23 +0300
committerMaxime Ripard <mripard@kernel.org>2024-01-29 16:20:23 +0300
commit4db102dcb0396a4ccf89b1eac0f4eb3fd167a080 (patch)
treeea47469abffb236c5ba305c8a406e1f8209c6f34 /drivers/video
parentaeb262c353354eab81ab0d3242afa70984b7dc34 (diff)
parent6613476e225e090cc9aad49be7fa504e290dd33d (diff)
downloadlinux-4db102dcb0396a4ccf89b1eac0f4eb3fd167a080.tar.xz
Merge drm/drm-next into drm-misc-next
Kickstart 6.9 development cycle. Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/backlight/Kconfig18
-rw-r--r--drivers/video/backlight/Makefile2
-rw-r--r--drivers/video/backlight/cr_bllcd.c264
-rw-r--r--drivers/video/backlight/hx8357.c74
-rw-r--r--drivers/video/backlight/ili922x.c8
-rw-r--r--drivers/video/backlight/lm3630a_bl.c2
-rw-r--r--drivers/video/backlight/lp855x_bl.c2
-rw-r--r--drivers/video/backlight/mp3309c.c444
-rw-r--r--drivers/video/backlight/pwm_bl.c46
-rw-r--r--drivers/video/console/Kconfig2
-rw-r--r--drivers/video/fbdev/Kconfig70
-rw-r--r--drivers/video/fbdev/Makefile2
-rw-r--r--drivers/video/fbdev/amba-clcd.c986
-rw-r--r--drivers/video/fbdev/core/fb_ddc.c1
-rw-r--r--drivers/video/fbdev/core/fb_defio.c8
-rw-r--r--drivers/video/fbdev/cyber2000fb.c1
-rw-r--r--drivers/video/fbdev/fsl-diu-fb.c2
-rw-r--r--drivers/video/fbdev/hgafb.c13
-rw-r--r--drivers/video/fbdev/hyperv_fb.c26
-rw-r--r--drivers/video/fbdev/i740fb.c1
-rw-r--r--drivers/video/fbdev/imxfb.c179
-rw-r--r--drivers/video/fbdev/intelfb/Makefile8
-rw-r--r--drivers/video/fbdev/intelfb/intelfb.h382
-rw-r--r--drivers/video/fbdev/intelfb/intelfb_i2c.c209
-rw-r--r--drivers/video/fbdev/intelfb/intelfbdrv.c1680
-rw-r--r--drivers/video/fbdev/intelfb/intelfbhw.c2115
-rw-r--r--drivers/video/fbdev/intelfb/intelfbhw.h609
-rw-r--r--drivers/video/fbdev/matrox/i2c-matroxfb.c15
-rw-r--r--drivers/video/fbdev/mmp/hw/mmp_spi.c2
-rw-r--r--drivers/video/fbdev/s3fb.c1
-rw-r--r--drivers/video/fbdev/sis/sis_main.c37
-rw-r--r--drivers/video/fbdev/ssd1307fb.c2
-rw-r--r--drivers/video/fbdev/stifb.c109
-rw-r--r--drivers/video/fbdev/tdfxfb.c1
-rw-r--r--drivers/video/fbdev/tridentfb.c1
-rw-r--r--drivers/video/fbdev/vermilion/Makefile6
-rw-r--r--drivers/video/fbdev/vermilion/cr_pll.c195
-rw-r--r--drivers/video/fbdev/vermilion/vermilion.c1175
-rw-r--r--drivers/video/fbdev/vermilion/vermilion.h245
-rw-r--r--drivers/video/fbdev/via/via_i2c.c1
-rw-r--r--drivers/video/logo/pnmtologo.c6
-rw-r--r--drivers/video/sticore.c5
42 files changed, 708 insertions, 8247 deletions
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 51387b1ef012..ea2d0d69bd8c 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -235,13 +235,6 @@ config BACKLIGHT_HP700
If you have an HP Jornada 700 series,
say Y to include backlight control driver.
-config BACKLIGHT_CARILLO_RANCH
- tristate "Intel Carillo Ranch Backlight Driver"
- depends on LCD_CLASS_DEVICE && PCI && X86 && FB_LE80578
- help
- If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
- backlight driver.
-
config BACKLIGHT_PWM
tristate "Generic PWM based Backlight Driver"
depends on PWM
@@ -402,6 +395,17 @@ config BACKLIGHT_LP8788
help
This supports TI LP8788 backlight driver.
+config BACKLIGHT_MP3309C
+ tristate "Backlight Driver for MPS MP3309C"
+ depends on I2C && PWM
+ select REGMAP_I2C
+ help
+ This supports MPS MP3309C backlight WLED driver in both PWM and
+ analog/I2C dimming modes.
+
+ To compile this driver as a module, choose M here: the module will
+ be called mp3309c.
+
config BACKLIGHT_PANDORA
tristate "Backlight driver for Pandora console"
depends on TWL4030_CORE
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index f72e1c3c59e9..06966cb20459 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_BACKLIGHT_ADP8870) += adp8870_bl.o
obj-$(CONFIG_BACKLIGHT_APPLE) += apple_bl.o
obj-$(CONFIG_BACKLIGHT_AS3711) += as3711_bl.o
obj-$(CONFIG_BACKLIGHT_BD6107) += bd6107.o
-obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o
obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o
@@ -44,6 +43,7 @@ obj-$(CONFIG_BACKLIGHT_LP855X) += lp855x_bl.o
obj-$(CONFIG_BACKLIGHT_LP8788) += lp8788_bl.o
obj-$(CONFIG_BACKLIGHT_LV5207LP) += lv5207lp.o
obj-$(CONFIG_BACKLIGHT_MAX8925) += max8925_bl.o
+obj-$(CONFIG_BACKLIGHT_MP3309C) += mp3309c.o
obj-$(CONFIG_BACKLIGHT_MT6370) += mt6370-backlight.o
obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
obj-$(CONFIG_BACKLIGHT_PANDORA) += pandora_bl.o
diff --git a/drivers/video/backlight/cr_bllcd.c b/drivers/video/backlight/cr_bllcd.c
deleted file mode 100644
index 781aeecc451d..000000000000
--- a/drivers/video/backlight/cr_bllcd.c
+++ /dev/null
@@ -1,264 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) Intel Corp. 2007.
- * All Rights Reserved.
- *
- * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- * develop this driver.
- *
- * This file is part of the Carillo Ranch video subsystem driver.
- *
- * Authors:
- * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- * Alan Hourihane <alanh-at-tungstengraphics-dot-com>
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/fb.h>
-#include <linux/backlight.h>
-#include <linux/lcd.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-/* The LVDS- and panel power controls sits on the
- * GPIO port of the ISA bridge.
- */
-
-#define CRVML_DEVICE_LPC 0x27B8
-#define CRVML_REG_GPIOBAR 0x48
-#define CRVML_REG_GPIOEN 0x4C
-#define CRVML_GPIOEN_BIT (1 << 4)
-#define CRVML_PANEL_PORT 0x38
-#define CRVML_LVDS_ON 0x00000001
-#define CRVML_PANEL_ON 0x00000002
-#define CRVML_BACKLIGHT_OFF 0x00000004
-
-/* The PLL Clock register sits on Host bridge */
-#define CRVML_DEVICE_MCH 0x5001
-#define CRVML_REG_MCHBAR 0x44
-#define CRVML_REG_MCHEN 0x54
-#define CRVML_MCHEN_BIT (1 << 28)
-#define CRVML_MCHMAP_SIZE 4096
-#define CRVML_REG_CLOCK 0xc3c
-#define CRVML_CLOCK_SHIFT 8
-#define CRVML_CLOCK_MASK 0x00000f00
-
-static struct pci_dev *lpc_dev;
-static u32 gpio_bar;
-
-struct cr_panel {
- struct backlight_device *cr_backlight_device;
- struct lcd_device *cr_lcd_device;
-};
-
-static int cr_backlight_set_intensity(struct backlight_device *bd)
-{
- u32 addr = gpio_bar + CRVML_PANEL_PORT;
- u32 cur = inl(addr);
-
- if (backlight_get_brightness(bd) == 0) {
- /* OFF */
- cur |= CRVML_BACKLIGHT_OFF;
- outl(cur, addr);
- } else {
- /* FULL ON */
- cur &= ~CRVML_BACKLIGHT_OFF;
- outl(cur, addr);
- }
-
- return 0;
-}
-
-static int cr_backlight_get_intensity(struct backlight_device *bd)
-{
- u32 addr = gpio_bar + CRVML_PANEL_PORT;
- u32 cur = inl(addr);
- u8 intensity;
-
- if (cur & CRVML_BACKLIGHT_OFF)
- intensity = 0;
- else
- intensity = 1;
-
- return intensity;
-}
-
-static const struct backlight_ops cr_backlight_ops = {
- .get_brightness = cr_backlight_get_intensity,
- .update_status = cr_backlight_set_intensity,
-};
-
-static void cr_panel_on(void)
-{
- u32 addr = gpio_bar + CRVML_PANEL_PORT;
- u32 cur = inl(addr);
-
- if (!(cur & CRVML_PANEL_ON)) {
- /* Make sure LVDS controller is down. */
- if (cur & 0x00000001) {
- cur &= ~CRVML_LVDS_ON;
- outl(cur, addr);
- }
- /* Power up Panel */
- schedule_timeout(HZ / 10);
- cur |= CRVML_PANEL_ON;
- outl(cur, addr);
- }
-
- /* Power up LVDS controller */
-
- if (!(cur & CRVML_LVDS_ON)) {
- schedule_timeout(HZ / 10);
- outl(cur | CRVML_LVDS_ON, addr);
- }
-}
-
-static void cr_panel_off(void)
-{
- u32 addr = gpio_bar + CRVML_PANEL_PORT;
- u32 cur = inl(addr);
-
- /* Power down LVDS controller first to avoid high currents */
- if (cur & CRVML_LVDS_ON) {
- cur &= ~CRVML_LVDS_ON;
- outl(cur, addr);
- }
- if (cur & CRVML_PANEL_ON) {
- schedule_timeout(HZ / 10);
- outl(cur & ~CRVML_PANEL_ON, addr);
- }
-}
-
-static int cr_lcd_set_power(struct lcd_device *ld, int power)
-{
- if (power == FB_BLANK_UNBLANK)
- cr_panel_on();
- if (power == FB_BLANK_POWERDOWN)
- cr_panel_off();
-
- return 0;
-}
-
-static struct lcd_ops cr_lcd_ops = {
- .set_power = cr_lcd_set_power,
-};
-
-static int cr_backlight_probe(struct platform_device *pdev)
-{
- struct backlight_properties props;
- struct backlight_device *bdp;
- struct lcd_device *ldp;
- struct cr_panel *crp;
- u8 dev_en;
-
- lpc_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
- CRVML_DEVICE_LPC, NULL);
- if (!lpc_dev) {
- pr_err("INTEL CARILLO RANCH LPC not found.\n");
- return -ENODEV;
- }
-
- pci_read_config_byte(lpc_dev, CRVML_REG_GPIOEN, &dev_en);
- if (!(dev_en & CRVML_GPIOEN_BIT)) {
- pr_err("Carillo Ranch GPIO device was not enabled.\n");
- pci_dev_put(lpc_dev);
- return -ENODEV;
- }
-
- memset(&props, 0, sizeof(struct backlight_properties));
- props.type = BACKLIGHT_RAW;
- bdp = devm_backlight_device_register(&pdev->dev, "cr-backlight",
- &pdev->dev, NULL, &cr_backlight_ops,
- &props);
- if (IS_ERR(bdp)) {
- pci_dev_put(lpc_dev);
- return PTR_ERR(bdp);
- }
-
- ldp = devm_lcd_device_register(&pdev->dev, "cr-lcd", &pdev->dev, NULL,
- &cr_lcd_ops);
- if (IS_ERR(ldp)) {
- pci_dev_put(lpc_dev);
- return PTR_ERR(ldp);
- }
-
- pci_read_config_dword(lpc_dev, CRVML_REG_GPIOBAR,
- &gpio_bar);
- gpio_bar &= ~0x3F;
-
- crp = devm_kzalloc(&pdev->dev, sizeof(*crp), GFP_KERNEL);
- if (!crp) {
- pci_dev_put(lpc_dev);
- return -ENOMEM;
- }
-
- crp->cr_backlight_device = bdp;
- crp->cr_lcd_device = ldp;
- crp->cr_backlight_device->props.power = FB_BLANK_UNBLANK;
- crp->cr_backlight_device->props.brightness = 0;
- cr_backlight_set_intensity(crp->cr_backlight_device);
- cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_UNBLANK);
-
- platform_set_drvdata(pdev, crp);
-
- return 0;
-}
-
-static void cr_backlight_remove(struct platform_device *pdev)
-{
- struct cr_panel *crp = platform_get_drvdata(pdev);
-
- crp->cr_backlight_device->props.power = FB_BLANK_POWERDOWN;
- crp->cr_backlight_device->props.brightness = 0;
- crp->cr_backlight_device->props.max_brightness = 0;
- cr_backlight_set_intensity(crp->cr_backlight_device);
- cr_lcd_set_power(crp->cr_lcd_device, FB_BLANK_POWERDOWN);
- pci_dev_put(lpc_dev);
-}
-
-static struct platform_driver cr_backlight_driver = {
- .probe = cr_backlight_probe,
- .remove_new = cr_backlight_remove,
- .driver = {
- .name = "cr_backlight",
- },
-};
-
-static struct platform_device *crp;
-
-static int __init cr_backlight_init(void)
-{
- int ret = platform_driver_register(&cr_backlight_driver);
-
- if (ret)
- return ret;
-
- crp = platform_device_register_simple("cr_backlight", -1, NULL, 0);
- if (IS_ERR(crp)) {
- platform_driver_unregister(&cr_backlight_driver);
- return PTR_ERR(crp);
- }
-
- pr_info("Carillo Ranch Backlight Driver Initialized.\n");
-
- return 0;
-}
-
-static void __exit cr_backlight_exit(void)
-{
- platform_device_unregister(crp);
- platform_driver_unregister(&cr_backlight_driver);
-}
-
-module_init(cr_backlight_init);
-module_exit(cr_backlight_exit);
-
-MODULE_AUTHOR("Tungsten Graphics Inc.");
-MODULE_DESCRIPTION("Carillo Ranch Backlight Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/hx8357.c b/drivers/video/backlight/hx8357.c
index f76d2469d490..d7298376cf74 100644
--- a/drivers/video/backlight/hx8357.c
+++ b/drivers/video/backlight/hx8357.c
@@ -6,11 +6,11 @@
*/
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
#include <linux/lcd.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#define HX8357_NUM_IM_PINS 3
@@ -83,11 +83,10 @@
#define HX8369_SET_GAMMA_CURVE_RELATED 0xe0
struct hx8357_data {
- unsigned im_pins[HX8357_NUM_IM_PINS];
- unsigned reset;
+ struct gpio_descs *im_pins;
+ struct gpio_desc *reset;
struct spi_device *spi;
int state;
- bool use_im_pins;
};
static u8 hx8357_seq_power[] = {
@@ -321,11 +320,11 @@ static void hx8357_lcd_reset(struct lcd_device *lcdev)
struct hx8357_data *lcd = lcd_get_data(lcdev);
/* Reset the screen */
- gpio_set_value(lcd->reset, 1);
+ gpiod_set_value(lcd->reset, 0);
usleep_range(10000, 12000);
- gpio_set_value(lcd->reset, 0);
+ gpiod_set_value(lcd->reset, 1);
usleep_range(10000, 12000);
- gpio_set_value(lcd->reset, 1);
+ gpiod_set_value(lcd->reset, 0);
/* The controller needs 120ms to recover from reset */
msleep(120);
@@ -340,10 +339,10 @@ static int hx8357_lcd_init(struct lcd_device *lcdev)
* Set the interface selection pins to SPI mode, with three
* wires
*/
- if (lcd->use_im_pins) {
- gpio_set_value_cansleep(lcd->im_pins[0], 1);
- gpio_set_value_cansleep(lcd->im_pins[1], 0);
- gpio_set_value_cansleep(lcd->im_pins[2], 1);
+ if (lcd->im_pins) {
+ gpiod_set_value_cansleep(lcd->im_pins->desc[0], 1);
+ gpiod_set_value_cansleep(lcd->im_pins->desc[1], 0);
+ gpiod_set_value_cansleep(lcd->im_pins->desc[2], 1);
}
ret = hx8357_spi_write_array(lcdev, hx8357_seq_power,
@@ -580,6 +579,7 @@ MODULE_DEVICE_TABLE(of, hx8357_dt_ids);
static int hx8357_probe(struct spi_device *spi)
{
+ struct device *dev = &spi->dev;
struct lcd_device *lcdev;
struct hx8357_data *lcd;
const struct of_device_id *match;
@@ -601,49 +601,19 @@ static int hx8357_probe(struct spi_device *spi)
if (!match || !match->data)
return -EINVAL;
- lcd->reset = of_get_named_gpio(spi->dev.of_node, "gpios-reset", 0);
- if (!gpio_is_valid(lcd->reset)) {
- dev_err(&spi->dev, "Missing dt property: gpios-reset\n");
- return -EINVAL;
- }
+ lcd->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(lcd->reset))
+ return dev_err_probe(dev, PTR_ERR(lcd->reset), "failed to request reset GPIO\n");
+ gpiod_set_consumer_name(lcd->reset, "hx8357-reset");
- ret = devm_gpio_request_one(&spi->dev, lcd->reset,
- GPIOF_OUT_INIT_HIGH,
- "hx8357-reset");
- if (ret) {
- dev_err(&spi->dev,
- "failed to request gpio %d: %d\n",
- lcd->reset, ret);
- return -EINVAL;
- }
+ lcd->im_pins = devm_gpiod_get_array_optional(dev, "im", GPIOD_OUT_LOW);
+ if (IS_ERR(lcd->im_pins))
+ return dev_err_probe(dev, PTR_ERR(lcd->im_pins), "failed to request im GPIOs\n");
+ if (lcd->im_pins->ndescs < HX8357_NUM_IM_PINS)
+ return dev_err_probe(dev, -EINVAL, "not enough im GPIOs\n");
- if (of_property_present(spi->dev.of_node, "im-gpios")) {
- lcd->use_im_pins = 1;
-
- for (i = 0; i < HX8357_NUM_IM_PINS; i++) {
- lcd->im_pins[i] = of_get_named_gpio(spi->dev.of_node,
- "im-gpios", i);
- if (lcd->im_pins[i] == -EPROBE_DEFER) {
- dev_info(&spi->dev, "GPIO requested is not here yet, deferring the probe\n");
- return -EPROBE_DEFER;
- }
- if (!gpio_is_valid(lcd->im_pins[i])) {
- dev_err(&spi->dev, "Missing dt property: im-gpios\n");
- return -EINVAL;
- }
-
- ret = devm_gpio_request_one(&spi->dev, lcd->im_pins[i],
- GPIOF_OUT_INIT_LOW,
- "im_pins");
- if (ret) {
- dev_err(&spi->dev, "failed to request gpio %d: %d\n",
- lcd->im_pins[i], ret);
- return -EINVAL;
- }
- }
- } else {
- lcd->use_im_pins = 0;
- }
+ for (i = 0; i < HX8357_NUM_IM_PINS; i++)
+ gpiod_set_consumer_name(lcd->im_pins->desc[i], "im_pins");
lcdev = devm_lcd_device_register(&spi->dev, "mxsfb", &spi->dev, lcd,
&hx8357_ops);
diff --git a/drivers/video/backlight/ili922x.c b/drivers/video/backlight/ili922x.c
index e7b6bd827986..c8e0e655dc86 100644
--- a/drivers/video/backlight/ili922x.c
+++ b/drivers/video/backlight/ili922x.c
@@ -81,7 +81,7 @@
#define START_RW_WRITE 0
#define START_RW_READ 1
-/**
+/*
* START_BYTE(id, rs, rw)
*
* Set the start byte according to the required operation.
@@ -100,7 +100,7 @@
#define START_BYTE(id, rs, rw) \
(0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
-/**
+/*
* CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
* for the SPI transfer. According to the datasheet, the controller
* accept higher frequency for the GRAM transfer, but it requires
@@ -269,6 +269,10 @@ static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
spi_message_add_tail(&xfer_regindex, &msg);
ret = spi_sync(spi, &msg);
+ if (ret < 0) {
+ dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
+ return ret;
+ }
spi_message_init(&msg);
tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
diff --git a/drivers/video/backlight/lm3630a_bl.c b/drivers/video/backlight/lm3630a_bl.c
index 8fcb62be597b..a3412c936ca2 100644
--- a/drivers/video/backlight/lm3630a_bl.c
+++ b/drivers/video/backlight/lm3630a_bl.c
@@ -180,7 +180,7 @@ static int lm3630a_pwm_ctrl(struct lm3630a_chip *pchip, int br, int br_max)
pchip->pwmd_state.enabled = pchip->pwmd_state.duty_cycle ? true : false;
- return pwm_apply_state(pchip->pwmd, &pchip->pwmd_state);
+ return pwm_apply_might_sleep(pchip->pwmd, &pchip->pwmd_state);
}
/* update and get brightness */
diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c
index da1f124db69c..7075bfab59c4 100644
--- a/drivers/video/backlight/lp855x_bl.c
+++ b/drivers/video/backlight/lp855x_bl.c
@@ -234,7 +234,7 @@ static int lp855x_pwm_ctrl(struct lp855x *lp, int br, int max_br)
state.duty_cycle = div_u64(br * state.period, max_br);
state.enabled = state.duty_cycle;
- return pwm_apply_state(lp->pwm, &state);
+ return pwm_apply_might_sleep(lp->pwm, &state);
}
static int lp855x_bl_update_status(struct backlight_device *bl)
diff --git a/drivers/video/backlight/mp3309c.c b/drivers/video/backlight/mp3309c.c
new file mode 100644
index 000000000000..34d71259fac1
--- /dev/null
+++ b/drivers/video/backlight/mp3309c.c
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for MPS MP3309C White LED driver with I2C interface
+ *
+ * This driver support both analog (by I2C commands) and PWM dimming control
+ * modes.
+ *
+ * Copyright (C) 2023 ASEM Srl
+ * Author: Flavio Suligoi <f.suligoi@asem.it>
+ *
+ * Based on pwm_bl.c
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+
+#define REG_I2C_0 0x00
+#define REG_I2C_1 0x01
+
+#define REG_I2C_0_EN 0x80
+#define REG_I2C_0_D0 0x40
+#define REG_I2C_0_D1 0x20
+#define REG_I2C_0_D2 0x10
+#define REG_I2C_0_D3 0x08
+#define REG_I2C_0_D4 0x04
+#define REG_I2C_0_RSRV1 0x02
+#define REG_I2C_0_RSRV2 0x01
+
+#define REG_I2C_1_RSRV1 0x80
+#define REG_I2C_1_DIMS 0x40
+#define REG_I2C_1_SYNC 0x20
+#define REG_I2C_1_OVP0 0x10
+#define REG_I2C_1_OVP1 0x08
+#define REG_I2C_1_VOS 0x04
+#define REG_I2C_1_LEDO 0x02
+#define REG_I2C_1_OTP 0x01
+
+#define ANALOG_I2C_NUM_LEVELS 32 /* 0..31 */
+#define ANALOG_I2C_REG_MASK 0x7c
+
+#define MP3309C_PWM_DEFAULT_NUM_LEVELS 256 /* 0..255 */
+
+enum mp3309c_status_value {
+ FIRST_POWER_ON,
+ BACKLIGHT_OFF,
+ BACKLIGHT_ON,
+};
+
+enum mp3309c_dimming_mode_value {
+ DIMMING_PWM,
+ DIMMING_ANALOG_I2C,
+};
+
+struct mp3309c_platform_data {
+ unsigned int max_brightness;
+ unsigned int default_brightness;
+ unsigned int *levels;
+ u8 dimming_mode;
+ u8 over_voltage_protection;
+ bool sync_mode;
+ u8 status;
+};
+
+struct mp3309c_chip {
+ struct device *dev;
+ struct mp3309c_platform_data *pdata;
+ struct backlight_device *bl;
+ struct gpio_desc *enable_gpio;
+ struct regmap *regmap;
+ struct pwm_device *pwmd;
+};
+
+static const struct regmap_config mp3309c_regmap = {
+ .name = "mp3309c_regmap",
+ .reg_bits = 8,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .max_register = REG_I2C_1,
+};
+
+static int mp3309c_enable_device(struct mp3309c_chip *chip)
+{
+ u8 reg_val;
+ int ret;
+
+ /* I2C register #0 - Device enable */
+ ret = regmap_update_bits(chip->regmap, REG_I2C_0, REG_I2C_0_EN,
+ REG_I2C_0_EN);
+ if (ret)
+ return ret;
+
+ /*
+ * I2C register #1 - Set working mode:
+ * - set one of the two dimming mode:
+ * - PWM dimming using an external PWM dimming signal
+ * - analog dimming using I2C commands
+ * - enable/disable synchronous mode
+ * - set overvoltage protection (OVP)
+ */
+ reg_val = 0x00;
+ if (chip->pdata->dimming_mode == DIMMING_PWM)
+ reg_val |= REG_I2C_1_DIMS;
+ if (chip->pdata->sync_mode)
+ reg_val |= REG_I2C_1_SYNC;
+ reg_val |= chip->pdata->over_voltage_protection;
+ ret = regmap_write(chip->regmap, REG_I2C_1, reg_val);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int mp3309c_bl_update_status(struct backlight_device *bl)
+{
+ struct mp3309c_chip *chip = bl_get_data(bl);
+ int brightness = backlight_get_brightness(bl);
+ struct pwm_state pwmstate;
+ unsigned int analog_val, bits_val;
+ int i, ret;
+
+ if (chip->pdata->dimming_mode == DIMMING_PWM) {
+ /*
+ * PWM control mode
+ */
+ pwm_get_state(chip->pwmd, &pwmstate);
+ pwm_set_relative_duty_cycle(&pwmstate,
+ chip->pdata->levels[brightness],
+ chip->pdata->levels[chip->pdata->max_brightness]);
+ pwmstate.enabled = true;
+ ret = pwm_apply_state(chip->pwmd, &pwmstate);
+ if (ret)
+ return ret;
+
+ switch (chip->pdata->status) {
+ case FIRST_POWER_ON:
+ case BACKLIGHT_OFF:
+ /*
+ * After 20ms of low pwm signal level, the chip turns
+ * off automatically. In this case, before enabling the
+ * chip again, we must wait about 10ms for pwm signal to
+ * stabilize.
+ */
+ if (brightness > 0) {
+ msleep(10);
+ mp3309c_enable_device(chip);
+ chip->pdata->status = BACKLIGHT_ON;
+ } else {
+ chip->pdata->status = BACKLIGHT_OFF;
+ }
+ break;
+ case BACKLIGHT_ON:
+ if (brightness == 0)
+ chip->pdata->status = BACKLIGHT_OFF;
+ break;
+ }
+ } else {
+ /*
+ * Analog (by I2C command) control mode
+ *
+ * The first time, before setting brightness, we must enable the
+ * device
+ */
+ if (chip->pdata->status == FIRST_POWER_ON)
+ mp3309c_enable_device(chip);
+
+ /*
+ * Dimming mode I2C command (fixed dimming range 0..31)
+ *
+ * The 5 bits of the dimming analog value D4..D0 is allocated
+ * in the I2C register #0, in the following way:
+ *
+ * +--+--+--+--+--+--+--+--+
+ * |EN|D0|D1|D2|D3|D4|XX|XX|
+ * +--+--+--+--+--+--+--+--+
+ */
+ analog_val = brightness;
+ bits_val = 0;
+ for (i = 0; i <= 5; i++)
+ bits_val += ((analog_val >> i) & 0x01) << (6 - i);
+ ret = regmap_update_bits(chip->regmap, REG_I2C_0,
+ ANALOG_I2C_REG_MASK, bits_val);
+ if (ret)
+ return ret;
+
+ if (brightness > 0)
+ chip->pdata->status = BACKLIGHT_ON;
+ else
+ chip->pdata->status = BACKLIGHT_OFF;
+ }
+
+ return 0;
+}
+
+static const struct backlight_ops mp3309c_bl_ops = {
+ .update_status = mp3309c_bl_update_status,
+};
+
+static int pm3309c_parse_dt_node(struct mp3309c_chip *chip,
+ struct mp3309c_platform_data *pdata)
+{
+ struct device_node *node = chip->dev->of_node;
+ struct property *prop_pwms;
+ struct property *prop_levels = NULL;
+ int length = 0;
+ int ret, i;
+ unsigned int num_levels, tmp_value;
+
+ if (!node) {
+ dev_err(chip->dev, "failed to get DT node\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Dimming mode: the MP3309C provides two dimming control mode:
+ *
+ * - PWM mode
+ * - Analog by I2C control mode (default)
+ *
+ * I2C control mode is assumed as default but, if the pwms property is
+ * found in the backlight node, the mode switches to PWM mode.
+ */
+ pdata->dimming_mode = DIMMING_ANALOG_I2C;
+ prop_pwms = of_find_property(node, "pwms", &length);
+ if (prop_pwms) {
+ chip->pwmd = devm_pwm_get(chip->dev, NULL);
+ if (IS_ERR(chip->pwmd))
+ return dev_err_probe(chip->dev, PTR_ERR(chip->pwmd),
+ "error getting pwm data\n");
+ pdata->dimming_mode = DIMMING_PWM;
+ pwm_apply_args(chip->pwmd);
+ }
+
+ /*
+ * In I2C control mode the dimming levels (0..31) are fixed by the
+ * hardware, while in PWM control mode they can be chosen by the user,
+ * to allow nonlinear mappings.
+ */
+ if (pdata->dimming_mode == DIMMING_ANALOG_I2C) {
+ /*
+ * Analog (by I2C commands) control mode: fixed 0..31 brightness
+ * levels
+ */
+ num_levels = ANALOG_I2C_NUM_LEVELS;
+
+ /* Enable GPIO used in I2C dimming mode only */
+ chip->enable_gpio = devm_gpiod_get(chip->dev, "enable",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(chip->enable_gpio))
+ return dev_err_probe(chip->dev,
+ PTR_ERR(chip->enable_gpio),
+ "error getting enable gpio\n");
+ } else {
+ /*
+ * PWM control mode: check for brightness level in DT
+ */
+ prop_levels = of_find_property(node, "brightness-levels",
+ &length);
+ if (prop_levels) {
+ /* Read brightness levels from DT */
+ num_levels = length / sizeof(u32);
+ if (num_levels < 2)
+ return -EINVAL;
+ } else {
+ /* Use default brightness levels */
+ num_levels = MP3309C_PWM_DEFAULT_NUM_LEVELS;
+ }
+ }
+
+ /* Fill brightness levels array */
+ pdata->levels = devm_kcalloc(chip->dev, num_levels,
+ sizeof(*pdata->levels), GFP_KERNEL);
+ if (!pdata->levels)
+ return -ENOMEM;
+ if (prop_levels) {
+ ret = of_property_read_u32_array(node, "brightness-levels",
+ pdata->levels,
+ num_levels);
+ if (ret < 0)
+ return ret;
+ } else {
+ for (i = 0; i < num_levels; i++)
+ pdata->levels[i] = i;
+ }
+
+ pdata->max_brightness = num_levels - 1;
+
+ ret = of_property_read_u32(node, "default-brightness",
+ &pdata->default_brightness);
+ if (ret)
+ pdata->default_brightness = pdata->max_brightness;
+ if (pdata->default_brightness > pdata->max_brightness) {
+ dev_err(chip->dev,
+ "default brightness exceeds max brightness\n");
+ pdata->default_brightness = pdata->max_brightness;
+ }
+
+ /*
+ * Over-voltage protection (OVP)
+ *
+ * This (optional) property values are:
+ *
+ * - 13.5V
+ * - 24V
+ * - 35.5V (hardware default setting)
+ *
+ * If missing, the default value for OVP is 35.5V
+ */
+ pdata->over_voltage_protection = REG_I2C_1_OVP1;
+ if (!of_property_read_u32(node, "mps,overvoltage-protection-microvolt",
+ &tmp_value)) {
+ switch (tmp_value) {
+ case 13500000:
+ pdata->over_voltage_protection = 0x00;
+ break;
+ case 24000000:
+ pdata->over_voltage_protection = REG_I2C_1_OVP0;
+ break;
+ case 35500000:
+ pdata->over_voltage_protection = REG_I2C_1_OVP1;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ /* Synchronous (default) and non-synchronous mode */
+ pdata->sync_mode = true;
+ if (of_property_read_bool(node, "mps,no-sync-mode"))
+ pdata->sync_mode = false;
+
+ return 0;
+}
+
+static int mp3309c_probe(struct i2c_client *client)
+{
+ struct mp3309c_platform_data *pdata = dev_get_platdata(&client->dev);
+ struct mp3309c_chip *chip;
+ struct backlight_properties props;
+ struct pwm_state pwmstate;
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ dev_err(&client->dev, "failed to check i2c functionality\n");
+ return -EOPNOTSUPP;
+ }
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->dev = &client->dev;
+
+ chip->regmap = devm_regmap_init_i2c(client, &mp3309c_regmap);
+ if (IS_ERR(chip->regmap))
+ return dev_err_probe(&client->dev, PTR_ERR(chip->regmap),
+ "failed to allocate register map\n");
+
+ i2c_set_clientdata(client, chip);
+
+ if (!pdata) {
+ pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ ret = pm3309c_parse_dt_node(chip, pdata);
+ if (ret)
+ return ret;
+ }
+ chip->pdata = pdata;
+
+ /* Backlight properties */
+ props.brightness = pdata->default_brightness;
+ props.max_brightness = pdata->max_brightness;
+ props.scale = BACKLIGHT_SCALE_LINEAR;
+ props.type = BACKLIGHT_RAW;
+ props.power = FB_BLANK_UNBLANK;
+ props.fb_blank = FB_BLANK_UNBLANK;
+ chip->bl = devm_backlight_device_register(chip->dev, "mp3309c",
+ chip->dev, chip,
+ &mp3309c_bl_ops, &props);
+ if (IS_ERR(chip->bl))
+ return dev_err_probe(chip->dev, PTR_ERR(chip->bl),
+ "error registering backlight device\n");
+
+ /* In PWM dimming mode, enable pwm device */
+ if (chip->pdata->dimming_mode == DIMMING_PWM) {
+ pwm_init_state(chip->pwmd, &pwmstate);
+ pwm_set_relative_duty_cycle(&pwmstate,
+ chip->pdata->default_brightness,
+ chip->pdata->max_brightness);
+ pwmstate.enabled = true;
+ ret = pwm_apply_state(chip->pwmd, &pwmstate);
+ if (ret)
+ return dev_err_probe(chip->dev, ret,
+ "error setting pwm device\n");
+ }
+
+ chip->pdata->status = FIRST_POWER_ON;
+ backlight_update_status(chip->bl);
+
+ return 0;
+}
+
+static void mp3309c_remove(struct i2c_client *client)
+{
+ struct mp3309c_chip *chip = i2c_get_clientdata(client);
+ struct backlight_device *bl = chip->bl;
+
+ bl->props.power = FB_BLANK_POWERDOWN;
+ bl->props.brightness = 0;
+ backlight_update_status(chip->bl);
+}
+
+static const struct of_device_id mp3309c_match_table[] = {
+ { .compatible = "mps,mp3309c", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mp3309c_match_table);
+
+static const struct i2c_device_id mp3309c_id[] = {
+ { "mp3309c", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, mp3309c_id);
+
+static struct i2c_driver mp3309c_i2c_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = mp3309c_match_table,
+ },
+ .probe = mp3309c_probe,
+ .remove = mp3309c_remove,
+ .id_table = mp3309c_id,
+};
+
+module_i2c_driver(mp3309c_i2c_driver);
+
+MODULE_DESCRIPTION("Backlight Driver for MPS MP3309C");
+MODULE_AUTHOR("Flavio Suligoi <f.suligoi@asem.it>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 289bd9ce4d36..ffcebf6aa76a 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -103,7 +103,7 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
pwm_get_state(pb->pwm, &state);
state.duty_cycle = compute_duty_cycle(pb, brightness, &state);
state.enabled = true;
- pwm_apply_state(pb->pwm, &state);
+ pwm_apply_might_sleep(pb->pwm, &state);
pwm_backlight_power_on(pb);
} else {
@@ -120,7 +120,7 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
* inactive output.
*/
state.enabled = !pb->power_supply && !pb->enable_gpio;
- pwm_apply_state(pb->pwm, &state);
+ pwm_apply_might_sleep(pb->pwm, &state);
}
if (pb->notify_after)
@@ -461,10 +461,9 @@ static int pwm_backlight_probe(struct platform_device *pdev)
if (!data) {
ret = pwm_backlight_parse_dt(&pdev->dev, &defdata);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to find platform data\n");
- return ret;
- }
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to find platform data\n");
data = &defdata;
}
@@ -493,24 +492,27 @@ static int pwm_backlight_probe(struct platform_device *pdev)
pb->enable_gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
GPIOD_ASIS);
if (IS_ERR(pb->enable_gpio)) {
- ret = PTR_ERR(pb->enable_gpio);
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(pb->enable_gpio),
+ "failed to acquire enable GPIO\n");
goto err_alloc;
}
pb->power_supply = devm_regulator_get_optional(&pdev->dev, "power");
if (IS_ERR(pb->power_supply)) {
ret = PTR_ERR(pb->power_supply);
- if (ret == -ENODEV)
+ if (ret == -ENODEV) {
pb->power_supply = NULL;
- else
+ } else {
+ dev_err_probe(&pdev->dev, ret,
+ "failed to acquire power regulator\n");
goto err_alloc;
+ }
}
pb->pwm = devm_pwm_get(&pdev->dev, NULL);
if (IS_ERR(pb->pwm)) {
- ret = PTR_ERR(pb->pwm);
- if (ret != -EPROBE_DEFER)
- dev_err(&pdev->dev, "unable to request PWM\n");
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(pb->pwm),
+ "unable to request PWM\n");
goto err_alloc;
}
@@ -528,10 +530,10 @@ static int pwm_backlight_probe(struct platform_device *pdev)
if (!state.period && (data->pwm_period_ns > 0))
state.period = data->pwm_period_ns;
- ret = pwm_apply_state(pb->pwm, &state);
+ ret = pwm_apply_might_sleep(pb->pwm, &state);
if (ret) {
- dev_err(&pdev->dev, "failed to apply initial PWM state: %d\n",
- ret);
+ dev_err_probe(&pdev->dev, ret,
+ "failed to apply initial PWM state");
goto err_alloc;
}
@@ -568,8 +570,8 @@ static int pwm_backlight_probe(struct platform_device *pdev)
ret = pwm_backlight_brightness_default(&pdev->dev, data,
state.period);
if (ret < 0) {
- dev_err(&pdev->dev,
- "failed to setup default brightness table\n");
+ dev_err_probe(&pdev->dev, ret,
+ "failed to setup default brightness table\n");
goto err_alloc;
}
@@ -597,8 +599,8 @@ static int pwm_backlight_probe(struct platform_device *pdev)
bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, pb,
&pwm_backlight_ops, &props);
if (IS_ERR(bl)) {
- dev_err(&pdev->dev, "failed to register backlight\n");
- ret = PTR_ERR(bl);
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(bl),
+ "failed to register backlight\n");
goto err_alloc;
}
@@ -633,7 +635,7 @@ static void pwm_backlight_remove(struct platform_device *pdev)
pwm_get_state(pb->pwm, &state);
state.duty_cycle = 0;
state.enabled = false;
- pwm_apply_state(pb->pwm, &state);
+ pwm_apply_might_sleep(pb->pwm, &state);
if (pb->exit)
pb->exit(&pdev->dev);
@@ -649,7 +651,7 @@ static void pwm_backlight_shutdown(struct platform_device *pdev)
pwm_get_state(pb->pwm, &state);
state.duty_cycle = 0;
state.enabled = false;
- pwm_apply_state(pb->pwm, &state);
+ pwm_apply_might_sleep(pb->pwm, &state);
}
#ifdef CONFIG_PM_SLEEP
@@ -673,7 +675,7 @@ static int pwm_backlight_suspend(struct device *dev)
pwm_get_state(pb->pwm, &state);
state.duty_cycle = 0;
state.enabled = false;
- pwm_apply_state(pb->pwm, &state);
+ pwm_apply_might_sleep(pb->pwm, &state);
if (pb->notify_after)
pb->notify_after(pb->dev, 0);
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 83c2d7329ca5..bc31db6ef7d2 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -7,7 +7,7 @@ menu "Console display driver support"
config VGA_CONSOLE
bool "VGA text console" if EXPERT || !X86
- depends on ALPHA || IA64 || X86 || \
+ depends on ALPHA || X86 || \
(ARM && ARCH_FOOTBRIDGE) || \
(MIPS && (MIPS_MALTA || SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80 || SNI_RM))
select APERTURE_HELPERS if (DRM || FB || VFIO_PCI_CORE)
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index f15ba4b2f306..a61b8260b8f3 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -114,24 +114,6 @@ config FB_PM2_FIFO_DISCONNECT
help
Support the Permedia2 FIFO disconnect feature.
-config FB_ARMCLCD
- tristate "ARM PrimeCell PL110 support"
- depends on ARM || ARM64 || COMPILE_TEST
- depends on FB && ARM_AMBA && HAS_IOMEM
- select FB_IOMEM_HELPERS
- select FB_MODE_HELPERS if OF
- select VIDEOMODE_HELPERS if OF
- select BACKLIGHT_CLASS_DEVICE if OF
- help
- This framebuffer device driver is for the ARM PrimeCell PL110
- Colour LCD controller. ARM PrimeCells provide the building
- blocks for System on a Chip devices.
-
- If you want to compile this as a module (=code which can be
- inserted into and removed from the running kernel), say M
- here and read <file:Documentation/kbuild/modules.rst>. The module
- will be called amba-clcd.
-
config FB_ACORN
bool "Acorn VIDC support"
depends on (FB = y) && ARM && ARCH_ACORN
@@ -825,58 +807,6 @@ config FB_I810_I2C
If unsure, say Y.
-config FB_LE80578
- tristate "Intel LE80578 (Vermilion) support"
- depends on FB && PCI && X86
- select FB_IOMEM_HELPERS
- select FB_MODE_HELPERS
- help
- This driver supports the LE80578 (Vermilion Range) chipset
-
-config FB_CARILLO_RANCH
- tristate "Intel Carillo Ranch support"
- depends on FB_LE80578 && FB && PCI && X86
- help
- This driver supports the LE80578 (Carillo Ranch) board
-
-config FB_INTEL
- tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support"
- depends on FB && PCI && X86 && AGP_INTEL && EXPERT
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- select FB_IOMEM_FOPS
- select FB_MODE_HELPERS
- select BOOT_VESA_SUPPORT if FB_INTEL = y
- depends on !DRM_I915
- help
- This driver supports the on-board graphics built in to the Intel
- 830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/965G/965GM chipsets.
- Say Y if you have and plan to use such a board.
-
- To make FB_INTEL=Y work you need to say AGP_INTEL=y too.
-
- To compile this driver as a module, choose M here: the
- module will be called intelfb.
-
- For more information, please read <file:Documentation/fb/intelfb.rst>
-
-config FB_INTEL_DEBUG
- bool "Intel driver Debug Messages"
- depends on FB_INTEL
- help
- Say Y here if you want the Intel driver to output all sorts
- of debugging information to provide to the maintainer when
- something goes wrong.
-
-config FB_INTEL_I2C
- bool "DDC/I2C for Intel framebuffer support"
- depends on FB_INTEL
- select FB_DDC
- default y
- help
- Say Y here if you want DDC/I2C support for your on-board Intel graphics.
-
config FB_MATROX
tristate "Matrox acceleration"
depends on FB && PCI
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
index 8e15220152bd..3eecd51267fa 100644
--- a/drivers/video/fbdev/Makefile
+++ b/drivers/video/fbdev/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_FB_IMSTT) += imsttfb.o
obj-$(CONFIG_FB_FM2) += fm2fb.o
obj-$(CONFIG_FB_VT8623) += vt8623fb.o
obj-$(CONFIG_FB_TRIDENT) += tridentfb.o
-obj-$(CONFIG_FB_LE80578) += vermilion/
obj-$(CONFIG_FB_S3) += s3fb.o
obj-$(CONFIG_FB_ARK) += arkfb.o
obj-$(CONFIG_FB_STI) += stifb.o
@@ -75,7 +74,6 @@ obj-$(CONFIG_FB_HIT) += hitfb.o
obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o
obj-$(CONFIG_FB_PVR2) += pvr2fb.o
obj-$(CONFIG_FB_VOODOO1) += sstfb.o
-obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o
obj-$(CONFIG_FB_GOLDFISH) += goldfishfb.o
obj-$(CONFIG_FB_68328) += 68328fb.o
obj-$(CONFIG_FB_GBE) += gbefb.o
diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c
deleted file mode 100644
index 47d373f04f3f..000000000000
--- a/drivers/video/fbdev/amba-clcd.c
+++ /dev/null
@@ -1,986 +0,0 @@
-/*
- * linux/drivers/video/amba-clcd.c
- *
- * Copyright (C) 2001 ARM Limited, by David A Rusling
- * Updated to 2.5, Deep Blue Solutions Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- *
- * ARM PrimeCell PL110 Color LCD Controller
- */
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/backlight.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/list.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_graph.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <video/display_timing.h>
-#include <video/of_display_timing.h>
-#include <video/videomode.h>
-
-#define to_clcd(info) container_of(info, struct clcd_fb, fb)
-
-/* This is limited to 16 characters when displayed by X startup */
-static const char *clcd_name = "CLCD FB";
-
-static inline void clcdfb_set_start(struct clcd_fb *fb)
-{
- unsigned long ustart = fb->fb.fix.smem_start;
- unsigned long lstart;
-
- ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
- lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
-
- writel(ustart, fb->regs + CLCD_UBAS);
- writel(lstart, fb->regs + CLCD_LBAS);
-}
-
-static void clcdfb_disable(struct clcd_fb *fb)
-{
- u32 val;
-
- if (fb->board->disable)
- fb->board->disable(fb);
-
- if (fb->panel->backlight) {
- fb->panel->backlight->props.power = FB_BLANK_POWERDOWN;
- backlight_update_status(fb->panel->backlight);
- }
-
- val = readl(fb->regs + fb->off_cntl);
- if (val & CNTL_LCDPWR) {
- val &= ~CNTL_LCDPWR;
- writel(val, fb->regs + fb->off_cntl);
-
- msleep(20);
- }
- if (val & CNTL_LCDEN) {
- val &= ~CNTL_LCDEN;
- writel(val, fb->regs + fb->off_cntl);
- }
-
- /*
- * Disable CLCD clock source.
- */
- if (fb->clk_enabled) {
- fb->clk_enabled = false;
- clk_disable(fb->clk);
- }
-}
-
-static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
-{
- /*
- * Enable the CLCD clock source.
- */
- if (!fb->clk_enabled) {
- fb->clk_enabled = true;
- clk_enable(fb->clk);
- }
-
- /*
- * Bring up by first enabling..
- */
- cntl |= CNTL_LCDEN;
- writel(cntl, fb->regs + fb->off_cntl);
-
- msleep(20);
-
- /*
- * and now apply power.
- */
- cntl |= CNTL_LCDPWR;
- writel(cntl, fb->regs + fb->off_cntl);
-
- /*
- * Turn on backlight
- */
- if (fb->panel->backlight) {
- fb->panel->backlight->props.power = FB_BLANK_UNBLANK;
- backlight_update_status(fb->panel->backlight);
- }
-
- /*
- * finally, enable the interface.
- */
- if (fb->board->enable)
- fb->board->enable(fb);
-}
-
-static int
-clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
-{
- u32 caps;
- int ret = 0;
-
- if (fb->panel->caps && fb->board->caps)
- caps = fb->panel->caps & fb->board->caps;
- else {
- /* Old way of specifying what can be used */
- caps = fb->panel->cntl & CNTL_BGR ?
- CLCD_CAP_BGR : CLCD_CAP_RGB;
- /* But mask out 444 modes as they weren't supported */
- caps &= ~CLCD_CAP_444;
- }
-
- /* Only TFT panels can do RGB888/BGR888 */
- if (!(fb->panel->cntl & CNTL_LCDTFT))
- caps &= ~CLCD_CAP_888;
-
- memset(&var->transp, 0, sizeof(var->transp));
-
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
-
- switch (var->bits_per_pixel) {
- case 1:
- case 2:
- case 4:
- case 8:
- /* If we can't do 5551, reject */
- caps &= CLCD_CAP_5551;
- if (!caps) {
- ret = -EINVAL;
- break;
- }
-
- var->red.length = var->bits_per_pixel;
- var->red.offset = 0;
- var->green.length = var->bits_per_pixel;
- var->green.offset = 0;
- var->blue.length = var->bits_per_pixel;
- var->blue.offset = 0;
- break;
-
- case 16:
- /* If we can't do 444, 5551 or 565, reject */
- if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
- ret = -EINVAL;
- break;
- }
-
- /*
- * Green length can be 4, 5 or 6 depending whether
- * we're operating in 444, 5551 or 565 mode.
- */
- if (var->green.length == 4 && caps & CLCD_CAP_444)
- caps &= CLCD_CAP_444;
- if (var->green.length == 5 && caps & CLCD_CAP_5551)
- caps &= CLCD_CAP_5551;
- else if (var->green.length == 6 && caps & CLCD_CAP_565)
- caps &= CLCD_CAP_565;
- else {
- /*
- * PL110 officially only supports RGB555,
- * but may be wired up to allow RGB565.
- */
- if (caps & CLCD_CAP_565) {
- var->green.length = 6;
- caps &= CLCD_CAP_565;
- } else if (caps & CLCD_CAP_5551) {
- var->green.length = 5;
- caps &= CLCD_CAP_5551;
- } else {
- var->green.length = 4;
- caps &= CLCD_CAP_444;
- }
- }
-
- if (var->green.length >= 5) {
- var->red.length = 5;
- var->blue.length = 5;
- } else {
- var->red.length = 4;
- var->blue.length = 4;
- }
- break;
- case 32:
- /* If we can't do 888, reject */
- caps &= CLCD_CAP_888;
- if (!caps) {
- ret = -EINVAL;
- break;
- }
-
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- /*
- * >= 16bpp displays have separate colour component bitfields
- * encoded in the pixel data. Calculate their position from
- * the bitfield length defined above.
- */
- if (ret == 0 && var->bits_per_pixel >= 16) {
- bool bgr, rgb;
-
- bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
- rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
-
- if (!bgr && !rgb)
- /*
- * The requested format was not possible, try just
- * our capabilities. One of BGR or RGB must be
- * supported.
- */
- bgr = caps & CLCD_CAP_BGR;
-
- if (bgr) {
- var->blue.offset = 0;
- var->green.offset = var->blue.offset + var->blue.length;
- var->red.offset = var->green.offset + var->green.length;
- } else {
- var->red.offset = 0;
- var->green.offset = var->red.offset + var->red.length;
- var->blue.offset = var->green.offset + var->green.length;
- }
- }
-
- return ret;
-}
-
-static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-{
- struct clcd_fb *fb = to_clcd(info);
- int ret = -EINVAL;
-
- if (fb->board->check)
- ret = fb->board->check(fb, var);
-
- if (ret == 0 &&
- var->xres_virtual * var->bits_per_pixel / 8 *
- var->yres_virtual > fb->fb.fix.smem_len)
- ret = -EINVAL;
-
- if (ret == 0)
- ret = clcdfb_set_bitfields(fb, var);
-
- return ret;
-}
-
-static int clcdfb_set_par(struct fb_info *info)
-{
- struct clcd_fb *fb = to_clcd(info);
- struct clcd_regs regs;
-
- fb->fb.fix.line_length = fb->fb.var.xres_virtual *
- fb->fb.var.bits_per_pixel / 8;
-
- if (fb->fb.var.bits_per_pixel <= 8)
- fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
- else
- fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
-
- fb->board->decode(fb, &regs);
-
- clcdfb_disable(fb);
-
- writel(regs.tim0, fb->regs + CLCD_TIM0);
- writel(regs.tim1, fb->regs + CLCD_TIM1);
- writel(regs.tim2, fb->regs + CLCD_TIM2);
- writel(regs.tim3, fb->regs + CLCD_TIM3);
-
- clcdfb_set_start(fb);
-
- clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
-
- fb->clcd_cntl = regs.cntl;
-
- clcdfb_enable(fb, regs.cntl);
-
-#ifdef DEBUG
- printk(KERN_INFO
- "CLCD: Registers set to\n"
- " %08x %08x %08x %08x\n"
- " %08x %08x %08x %08x\n",
- readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
- readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
- readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
- readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
-#endif
-
- return 0;
-}
-
-static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
-{
- unsigned int mask = (1 << bf->length) - 1;
-
- return (val >> (16 - bf->length) & mask) << bf->offset;
-}
-
-/*
- * Set a single color register. The values supplied have a 16 bit
- * magnitude. Return != 0 for invalid regno.
- */
-static int
-clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
- unsigned int blue, unsigned int transp, struct fb_info *info)
-{
- struct clcd_fb *fb = to_clcd(info);
-
- if (regno < 16)
- fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
- convert_bitfield(blue, &fb->fb.var.blue) |
- convert_bitfield(green, &fb->fb.var.green) |
- convert_bitfield(red, &fb->fb.var.red);
-
- if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
- int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
- u32 val, mask, newval;
-
- newval = (red >> 11) & 0x001f;
- newval |= (green >> 6) & 0x03e0;
- newval |= (blue >> 1) & 0x7c00;
-
- /*
- * 3.2.11: if we're configured for big endian
- * byte order, the palette entries are swapped.
- */
- if (fb->clcd_cntl & CNTL_BEBO)
- regno ^= 1;
-
- if (regno & 1) {
- newval <<= 16;
- mask = 0x0000ffff;
- } else {
- mask = 0xffff0000;
- }
-
- val = readl(fb->regs + hw_reg) & mask;
- writel(val | newval, fb->regs + hw_reg);
- }
-
- return regno > 255;
-}
-
-/*
- * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
- * then the caller blanks by setting the CLUT (Color Look Up Table) to all
- * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
- * to e.g. a video mode which doesn't support it. Implements VESA suspend
- * and powerdown modes on hardware that supports disabling hsync/vsync:
- * blank_mode == 2: suspend vsync
- * blank_mode == 3: suspend hsync
- * blank_mode == 4: powerdown
- */
-static int clcdfb_blank(int blank_mode, struct fb_info *info)
-{
- struct clcd_fb *fb = to_clcd(info);
-
- if (blank_mode != 0) {
- clcdfb_disable(fb);
- } else {
- clcdfb_enable(fb, fb->clcd_cntl);
- }
- return 0;
-}
-
-static int clcdfb_mmap(struct fb_info *info,
- struct vm_area_struct *vma)
-{
- struct clcd_fb *fb = to_clcd(info);
- unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
- int ret = -EINVAL;
-
- len = info->fix.smem_len;
-
- if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
- fb->board->mmap)
- ret = fb->board->mmap(fb, vma);
-
- return ret;
-}
-
-static const struct fb_ops clcdfb_ops = {
- .owner = THIS_MODULE,
- __FB_DEFAULT_IOMEM_OPS_RDWR,
- .fb_check_var = clcdfb_check_var,
- .fb_set_par = clcdfb_set_par,
- .fb_setcolreg = clcdfb_setcolreg,
- .fb_blank = clcdfb_blank,
- __FB_DEFAULT_IOMEM_OPS_DRAW,
- .fb_mmap = clcdfb_mmap,
-};
-
-static int clcdfb_register(struct clcd_fb *fb)
-{
- int ret;
-
- /*
- * ARM PL111 always has IENB at 0x1c; it's only PL110
- * which is reversed on some platforms.
- */
- if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
- fb->off_ienb = CLCD_PL111_IENB;
- fb->off_cntl = CLCD_PL111_CNTL;
- } else {
- fb->off_ienb = CLCD_PL110_IENB;
- fb->off_cntl = CLCD_PL110_CNTL;
- }
-
- fb->clk = clk_get(&fb->dev->dev, NULL);
- if (IS_ERR(fb->clk)) {
- ret = PTR_ERR(fb->clk);
- goto out;
- }
-
- ret = clk_prepare(fb->clk);
- if (ret)
- goto free_clk;
-
- fb->fb.device = &fb->dev->dev;
-
- fb->fb.fix.mmio_start = fb->dev->res.start;
- fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
-
- fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
- if (!fb->regs) {
- printk(KERN_ERR "CLCD: unable to remap registers\n");
- ret = -ENOMEM;
- goto clk_unprep;
- }
-
- fb->fb.fbops = &clcdfb_ops;
- fb->fb.pseudo_palette = fb->cmap;
-
- strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
- fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
- fb->fb.fix.type_aux = 0;
- fb->fb.fix.xpanstep = 0;
- fb->fb.fix.ypanstep = 0;
- fb->fb.fix.ywrapstep = 0;
- fb->fb.fix.accel = FB_ACCEL_NONE;
-
- fb->fb.var.xres = fb->panel->mode.xres;
- fb->fb.var.yres = fb->panel->mode.yres;
- fb->fb.var.xres_virtual = fb->panel->mode.xres;
- fb->fb.var.yres_virtual = fb->panel->mode.yres;
- fb->fb.var.bits_per_pixel = fb->panel->bpp;
- fb->fb.var.grayscale = fb->panel->grayscale;
- fb->fb.var.pixclock = fb->panel->mode.pixclock;
- fb->fb.var.left_margin = fb->panel->mode.left_margin;
- fb->fb.var.right_margin = fb->panel->mode.right_margin;
- fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
- fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
- fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
- fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
- fb->fb.var.sync = fb->panel->mode.sync;
- fb->fb.var.vmode = fb->panel->mode.vmode;
- fb->fb.var.activate = FB_ACTIVATE_NOW;
- fb->fb.var.nonstd = 0;
- fb->fb.var.height = fb->panel->height;
- fb->fb.var.width = fb->panel->width;
- fb->fb.var.accel_flags = 0;
-
- fb->fb.monspecs.hfmin = 0;
- fb->fb.monspecs.hfmax = 100000;
- fb->fb.monspecs.vfmin = 0;
- fb->fb.monspecs.vfmax = 400;
- fb->fb.monspecs.dclkmin = 1000000;
- fb->fb.monspecs.dclkmax = 100000000;
-
- /*
- * Make sure that the bitfields are set appropriately.
- */
- clcdfb_set_bitfields(fb, &fb->fb.var);
-
- /*
- * Allocate colourmap.
- */
- ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
- if (ret)
- goto unmap;
-
- /*
- * Ensure interrupts are disabled.
- */
- writel(0, fb->regs + fb->off_ienb);
-
- fb_set_var(&fb->fb, &fb->fb.var);
-
- dev_info(&fb->dev->dev, "%s hardware, %s display\n",
- fb->board->name, fb->panel->mode.name);
-
- ret = register_framebuffer(&fb->fb);
- if (ret == 0)
- goto out;
-
- printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
-
- fb_dealloc_cmap(&fb->fb.cmap);
- unmap:
- iounmap(fb->regs);
- clk_unprep:
- clk_unprepare(fb->clk);
- free_clk:
- clk_put(fb->clk);
- out:
- return ret;
-}
-
-#ifdef CONFIG_OF
-static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
- struct clcd_panel *clcd_panel)
-{
- int err;
- struct display_timing timing;
- struct videomode video;
-
- err = of_get_display_timing(node, "panel-timing", &timing);
- if (err) {
- pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
- return err;
- }
-
- videomode_from_timing(&timing, &video);
-
- err = fb_videomode_from_videomode(&video, &clcd_panel->mode);
- if (err)
- return err;
-
- /* Set up some inversion flags */
- if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
- clcd_panel->tim2 |= TIM2_IPC;
- else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE))
- /*
- * To preserve backwards compatibility, the IPC (inverted
- * pixel clock) flag needs to be set on any display that
- * doesn't explicitly specify that the pixel clock is
- * active on the negative or positive edge.
- */
- clcd_panel->tim2 |= TIM2_IPC;
-
- if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
- clcd_panel->tim2 |= TIM2_IHS;
-
- if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
- clcd_panel->tim2 |= TIM2_IVS;
-
- if (timing.flags & DISPLAY_FLAGS_DE_LOW)
- clcd_panel->tim2 |= TIM2_IOE;
-
- return 0;
-}
-
-static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
-{
- return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
- mode->refresh);
-}
-
-static int clcdfb_of_get_backlight(struct device *dev,
- struct clcd_panel *clcd_panel)
-{
- struct backlight_device *backlight;
-
- /* Look up the optional backlight device */
- backlight = devm_of_find_backlight(dev);
- if (IS_ERR(backlight))
- return PTR_ERR(backlight);
-
- clcd_panel->backlight = backlight;
- return 0;
-}
-
-static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel,
- struct clcd_panel *clcd_panel)
-{
- int err;
- struct fb_videomode *mode;
- char *name;
- int len;
-
- /* Only directly connected DPI panels supported for now */
- if (of_device_is_compatible(panel, "panel-dpi"))
- err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel);
- else
- err = -ENOENT;
- if (err)
- return err;
- mode = &clcd_panel->mode;
-
- len = clcdfb_snprintf_mode(NULL, 0, mode);
- name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
- if (!name)
- return -ENOMEM;
-
- clcdfb_snprintf_mode(name, len + 1, mode);
- mode->name = name;
-
- return 0;
-}
-
-static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
-{
- static struct {
- unsigned int part;
- u32 r0, g0, b0;
- u32 caps;
- } panels[] = {
- { 0x110, 1, 7, 13, CLCD_CAP_5551 },
- { 0x110, 0, 8, 16, CLCD_CAP_888 },
- { 0x110, 16, 8, 0, CLCD_CAP_888 },
- { 0x111, 4, 14, 20, CLCD_CAP_444 },
- { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
- { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
- CLCD_CAP_565 },
- { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
- CLCD_CAP_565 | CLCD_CAP_888 },
- };
- int i;
-
- /* Bypass pixel clock divider */
- fb->panel->tim2 |= TIM2_BCD;
-
- /* TFT display, vert. comp. interrupt at the start of the back porch */
- fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
-
- fb->panel->caps = 0;
-
- /* Match the setup with known variants */
- for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
- if (amba_part(fb->dev) != panels[i].part)
- continue;
- if (g0 != panels[i].g0)
- continue;
- if (r0 == panels[i].r0 && b0 == panels[i].b0)
- fb->panel->caps = panels[i].caps;
- }
-
- /*
- * If we actually physically connected the R lines to B and
- * vice versa
- */
- if (r0 != 0 && b0 == 0)
- fb->panel->bgr_connection = true;
-
- return fb->panel->caps ? 0 : -EINVAL;
-}
-
-static int clcdfb_of_init_display(struct clcd_fb *fb)
-{
- struct device_node *endpoint, *panel;
- int err;
- unsigned int bpp;
- u32 max_bandwidth;
- u32 tft_r0b0g0[3];
-
- fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
- if (!fb->panel)
- return -ENOMEM;
-
- /*
- * Fetch the panel endpoint.
- */
- endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
- if (!endpoint)
- return -ENODEV;
-
- panel = of_graph_get_remote_port_parent(endpoint);
- if (!panel) {
- err = -ENODEV;
- goto out_endpoint_put;
- }
-
- err = clcdfb_of_get_backlight(&fb->dev->dev, fb->panel);
- if (err)
- goto out_panel_put;
-
- err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel);
- if (err)
- goto out_panel_put;
-
- err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
- &max_bandwidth);
- if (!err) {
- /*
- * max_bandwidth is in bytes per second and pixclock in
- * pico-seconds, so the maximum allowed bits per pixel is
- * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
- * Rearrange this calculation to avoid overflow and then ensure
- * result is a valid format.
- */
- bpp = max_bandwidth / (1000 / 8)
- / PICOS2KHZ(fb->panel->mode.pixclock);
- bpp = rounddown_pow_of_two(bpp);
- if (bpp > 32)
- bpp = 32;
- } else
- bpp = 32;
- fb->panel->bpp = bpp;
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
- fb->panel->cntl |= CNTL_BEBO;
-#endif
- fb->panel->width = -1;
- fb->panel->height = -1;
-
- if (of_property_read_u32_array(endpoint,
- "arm,pl11x,tft-r0g0b0-pads",
- tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0) {
- err = -ENOENT;
- goto out_panel_put;
- }
-
- of_node_put(panel);
- of_node_put(endpoint);
-
- return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
- tft_r0b0g0[1], tft_r0b0g0[2]);
-out_panel_put:
- of_node_put(panel);
-out_endpoint_put:
- of_node_put(endpoint);
- return err;
-}
-
-static int clcdfb_of_vram_setup(struct clcd_fb *fb)
-{
- int err;
- struct device_node *memory;
- u64 size;
-
- err = clcdfb_of_init_display(fb);
- if (err)
- return err;
-
- memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
- if (!memory)
- return -ENODEV;
-
- fb->fb.screen_base = of_iomap(memory, 0);
- if (!fb->fb.screen_base) {
- of_node_put(memory);
- return -ENOMEM;
- }
-
- fb->fb.fix.smem_start = of_translate_address(memory,
- of_get_address(memory, 0, &size, NULL));
- fb->fb.fix.smem_len = size;
- of_node_put(memory);
-
- return 0;
-}
-
-static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
- unsigned long off, user_size, kernel_size;
-
-
- off = vma->vm_pgoff << PAGE_SHIFT;
- user_size = vma->vm_end - vma->vm_start;
- kernel_size = fb->fb.fix.smem_len;
-
- if (off >= kernel_size || user_size > (kernel_size - off))
- return -ENXIO;
-
- return remap_pfn_range(vma, vma->vm_start,
- __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
- user_size,
- pgprot_writecombine(vma->vm_page_prot));
-}
-
-static void clcdfb_of_vram_remove(struct clcd_fb *fb)
-{
- iounmap(fb->fb.screen_base);
-}
-
-static int clcdfb_of_dma_setup(struct clcd_fb *fb)
-{
- unsigned long framesize;
- dma_addr_t dma;
- int err;
-
- err = clcdfb_of_init_display(fb);
- if (err)
- return err;
-
- framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres *
- fb->panel->bpp / 8);
- fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
- &dma, GFP_KERNEL);
- if (!fb->fb.screen_base)
- return -ENOMEM;
-
- fb->fb.fix.smem_start = dma;
- fb->fb.fix.smem_len = framesize;
-
- return 0;
-}
-
-static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
- vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
-
- return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-}
-
-static void clcdfb_of_dma_remove(struct clcd_fb *fb)
-{
- dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
- fb->fb.screen_base, fb->fb.fix.smem_start);
-}
-
-static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
-{
- struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
- GFP_KERNEL);
- struct device_node *node = dev->dev.of_node;
-
- if (!board)
- return NULL;
-
- board->name = of_node_full_name(node);
- board->caps = CLCD_CAP_ALL;
- board->check = clcdfb_check;
- board->decode = clcdfb_decode;
- if (of_property_present(node, "memory-region")) {
- board->setup = clcdfb_of_vram_setup;
- board->mmap = clcdfb_of_vram_mmap;
- board->remove = clcdfb_of_vram_remove;
- } else {
- board->setup = clcdfb_of_dma_setup;
- board->mmap = clcdfb_of_dma_mmap;
- board->remove = clcdfb_of_dma_remove;
- }
-
- return board;
-}
-#else
-static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
-{
- return NULL;
-}
-#endif
-
-static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
-{
- struct clcd_board *board = dev_get_platdata(&dev->dev);
- struct clcd_fb *fb;
- int ret;
-
- if (!board)
- board = clcdfb_of_get_board(dev);
-
- if (!board)
- return -EINVAL;
-
- ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
- if (ret)
- goto out;
-
- ret = amba_request_regions(dev, NULL);
- if (ret) {
- printk(KERN_ERR "CLCD: unable to reserve regs region\n");
- goto out;
- }
-
- fb = kzalloc(sizeof(*fb), GFP_KERNEL);
- if (!fb) {
- ret = -ENOMEM;
- goto free_region;
- }
-
- fb->dev = dev;
- fb->board = board;
-
- dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n",
- amba_part(dev), amba_manf(dev), amba_rev(dev),
- (unsigned long long)dev->res.start);
-
- ret = fb->board->setup(fb);
- if (ret)
- goto free_fb;
-
- ret = clcdfb_register(fb);
- if (ret == 0) {
- amba_set_drvdata(dev, fb);
- goto out;
- }
-
- fb->board->remove(fb);
- free_fb:
- kfree(fb);
- free_region:
- amba_release_regions(dev);
- out:
- return ret;
-}
-
-static void clcdfb_remove(struct amba_device *dev)
-{
- struct clcd_fb *fb = amba_get_drvdata(dev);
-
- clcdfb_disable(fb);
- unregister_framebuffer(&fb->fb);
- if (fb->fb.cmap.len)
- fb_dealloc_cmap(&fb->fb.cmap);
- iounmap(fb->regs);
- clk_unprepare(fb->clk);
- clk_put(fb->clk);
-
- fb->board->remove(fb);
-
- kfree(fb);
-
- amba_release_regions(dev);
-}
-
-static const struct amba_id clcdfb_id_table[] = {
- {
- .id = 0x00041110,
- .mask = 0x000ffffe,
- },
- { 0, 0 },
-};
-
-MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
-
-static struct amba_driver clcd_driver = {
- .drv = {
- .name = "clcd-pl11x",
- },
- .probe = clcdfb_probe,
- .remove = clcdfb_remove,
- .id_table = clcdfb_id_table,
-};
-
-static int __init amba_clcdfb_init(void)
-{
- if (fb_get_options("ambafb", NULL))
- return -ENODEV;
-
- return amba_driver_register(&clcd_driver);
-}
-
-module_init(amba_clcdfb_init);
-
-static void __exit amba_clcdfb_exit(void)
-{
- amba_driver_unregister(&clcd_driver);
-}
-
-module_exit(amba_clcdfb_exit);
-
-MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/core/fb_ddc.c b/drivers/video/fbdev/core/fb_ddc.c
index 8bf5f2f54be7..e25143219862 100644
--- a/drivers/video/fbdev/core/fb_ddc.c
+++ b/drivers/video/fbdev/core/fb_ddc.c
@@ -116,7 +116,6 @@ unsigned char *fb_ddc_read(struct i2c_adapter *adapter)
algo_data->setsda(algo_data->data, 1);
algo_data->setscl(algo_data->data, 1);
- adapter->class |= I2C_CLASS_DDC;
return edid;
}
diff --git a/drivers/video/fbdev/core/fb_defio.c b/drivers/video/fbdev/core/fb_defio.c
index 1b0b85e59e5e..dae96c9f61cf 100644
--- a/drivers/video/fbdev/core/fb_defio.c
+++ b/drivers/video/fbdev/core/fb_defio.c
@@ -132,11 +132,7 @@ int fb_deferred_io_fsync(struct file *file, loff_t start, loff_t end, int datasy
return 0;
inode_lock(inode);
- /* Kill off the delayed work */
- cancel_delayed_work_sync(&info->deferred_work);
-
- /* Run it immediately */
- schedule_delayed_work(&info->deferred_work, 0);
+ flush_delayed_work(&info->deferred_work);
inode_unlock(inode);
return 0;
@@ -319,7 +315,7 @@ static void fb_deferred_io_lastclose(struct fb_info *info)
struct page *page;
int i;
- cancel_delayed_work_sync(&info->deferred_work);
+ flush_delayed_work(&info->deferred_work);
/* clear out the mapping that we setup */
for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) {
diff --git a/drivers/video/fbdev/cyber2000fb.c b/drivers/video/fbdev/cyber2000fb.c
index abb87d3576db..986760b90465 100644
--- a/drivers/video/fbdev/cyber2000fb.c
+++ b/drivers/video/fbdev/cyber2000fb.c
@@ -1227,7 +1227,6 @@ static int cyber2000fb_setup_ddc_bus(struct cfb_info *cfb)
strscpy(cfb->ddc_adapter.name, cfb->fb.fix.id,
sizeof(cfb->ddc_adapter.name));
cfb->ddc_adapter.owner = THIS_MODULE;
- cfb->ddc_adapter.class = I2C_CLASS_DDC;
cfb->ddc_adapter.algo_data = &cfb->ddc_algo;
cfb->ddc_adapter.dev.parent = cfb->fb.device;
cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda;
diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c
index 0bced82fa494..0191141657fd 100644
--- a/drivers/video/fbdev/fsl-diu-fb.c
+++ b/drivers/video/fbdev/fsl-diu-fb.c
@@ -877,7 +877,7 @@ static int map_video_memory(struct fb_info *info)
}
mutex_lock(&info->mm_lock);
info->screen_base = p;
- info->fix.smem_start = virt_to_phys(info->screen_base);
+ info->fix.smem_start = virt_to_phys((__force const void *)info->screen_base);
info->fix.smem_len = smem_len;
mutex_unlock(&info->mm_lock);
info->screen_size = info->fix.smem_len;
diff --git a/drivers/video/fbdev/hgafb.c b/drivers/video/fbdev/hgafb.c
index 10728259dac2..264c8cedba15 100644
--- a/drivers/video/fbdev/hgafb.c
+++ b/drivers/video/fbdev/hgafb.c
@@ -364,6 +364,8 @@ error:
* hgafb_open - open the framebuffer device
* @info: pointer to fb_info object containing info for current hga board
* @init: open by console system or userland.
+ *
+ * Returns: %0
*/
static int hgafb_open(struct fb_info *info, int init)
@@ -378,6 +380,8 @@ static int hgafb_open(struct fb_info *info, int init)
* hgafb_release - open the framebuffer device
* @info: pointer to fb_info object containing info for current hga board
* @init: open by console system or userland.
+ *
+ * Returns: %0
*/
static int hgafb_release(struct fb_info *info, int init)
@@ -399,6 +403,8 @@ static int hgafb_release(struct fb_info *info, int init)
* This callback function is used to set the color registers of a HGA
* board. Since we have only two fixed colors only @regno is checked.
* A zero is returned on success and 1 for failure.
+ *
+ * Returns: %0
*/
static int hgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
@@ -410,14 +416,15 @@ static int hgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
}
/**
- * hga_pan_display - pan or wrap the display
+ * hgafb_pan_display - pan or wrap the display
* @var:contains new xoffset, yoffset and vmode values
* @info:pointer to fb_info object containing info for current hga board
*
* This function looks only at xoffset, yoffset and the %FB_VMODE_YWRAP
* flag in @var. If input parameters are correct it calls hga_pan() to
* program the hardware. @info->var is updated to the new values.
- * A zero is returned on success and %-EINVAL for failure.
+ *
+ * Returns: %0 on success or %-EINVAL for failure.
*/
static int hgafb_pan_display(struct fb_var_screeninfo *var,
@@ -449,6 +456,8 @@ static int hgafb_pan_display(struct fb_var_screeninfo *var,
* @blank_mode == 2 means suspend vsync,
* @blank_mode == 3 means suspend hsync,
* @blank_mode == 4 means powerdown.
+ *
+ * Returns: %0
*/
static int hgafb_blank(int blank_mode, struct fb_info *info)
diff --git a/drivers/video/fbdev/hyperv_fb.c b/drivers/video/fbdev/hyperv_fb.c
index a80939fe2ee6..c26ee6fd73c9 100644
--- a/drivers/video/fbdev/hyperv_fb.c
+++ b/drivers/video/fbdev/hyperv_fb.c
@@ -48,7 +48,6 @@
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
-#include <linux/screen_info.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/completion.h>
@@ -927,8 +926,8 @@ static phys_addr_t hvfb_get_phymem(struct hv_device *hdev,
if (request_size == 0)
return -1;
- if (order <= MAX_ORDER) {
- /* Call alloc_pages if the size is less than 2^MAX_ORDER */
+ if (order <= MAX_PAGE_ORDER) {
+ /* Call alloc_pages if the size is less than 2^MAX_PAGE_ORDER */
page = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
if (!page)
return -1;
@@ -958,7 +957,7 @@ static void hvfb_release_phymem(struct hv_device *hdev,
{
unsigned int order = get_order(size);
- if (order <= MAX_ORDER)
+ if (order <= MAX_PAGE_ORDER)
__free_pages(pfn_to_page(paddr >> PAGE_SHIFT), order);
else
dma_free_coherent(&hdev->device,
@@ -975,7 +974,8 @@ static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info)
struct pci_dev *pdev = NULL;
void __iomem *fb_virt;
int gen2vm = efi_enabled(EFI_BOOT);
- resource_size_t base, size;
+ resource_size_t base = 0;
+ resource_size_t size = 0;
phys_addr_t paddr;
int ret;
@@ -1010,9 +1010,6 @@ static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info)
goto getmem_done;
}
pr_info("Unable to allocate enough contiguous physical memory on Gen 1 VM. Using MMIO instead.\n");
- } else if (IS_ENABLED(CONFIG_SYSFB)) {
- base = screen_info.lfb_base;
- size = screen_info.lfb_size;
} else {
goto err1;
}
@@ -1056,16 +1053,13 @@ static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info)
info->screen_size = dio_fb_size;
getmem_done:
- aperture_remove_conflicting_devices(base, size, KBUILD_MODNAME);
+ if (base && size)
+ aperture_remove_conflicting_devices(base, size, KBUILD_MODNAME);
+ else
+ aperture_remove_all_conflicting_devices(KBUILD_MODNAME);
- if (!gen2vm) {
+ if (!gen2vm)
pci_dev_put(pdev);
- } else if (IS_ENABLED(CONFIG_SYSFB)) {
- /* framebuffer is reallocated, clear screen_info to avoid misuse from kexec */
- screen_info.lfb_size = 0;
- screen_info.lfb_base = 0;
- screen_info.orig_video_isVGA = 0;
- }
return 0;
diff --git a/drivers/video/fbdev/i740fb.c b/drivers/video/fbdev/i740fb.c
index 1897e65ab703..9b74dae71472 100644
--- a/drivers/video/fbdev/i740fb.c
+++ b/drivers/video/fbdev/i740fb.c
@@ -163,7 +163,6 @@ static int i740fb_setup_ddc_bus(struct fb_info *info)
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
- par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
par->ddc_algo.setsda = i740fb_ddc_setsda;
diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c
index 84201c9608d3..a4dbc72f93c3 100644
--- a/drivers/video/fbdev/imxfb.c
+++ b/drivers/video/fbdev/imxfb.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Freescale i.MX Frame Buffer device driver
*
* Copyright (C) 2004 Sascha Hauer, Pengutronix
* Based on acornfb.c Copyright (C) Russell King.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- *
* Please direct your questions and comments on this driver to the following
* email address:
*
@@ -34,6 +31,7 @@
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/bitfield.h>
#include <linux/regulator/consumer.h>
@@ -41,12 +39,6 @@
#include <video/of_videomode.h>
#include <video/videomode.h>
-#define PCR_TFT (1 << 31)
-#define PCR_BPIX_8 (3 << 25)
-#define PCR_BPIX_12 (4 << 25)
-#define PCR_BPIX_16 (5 << 25)
-#define PCR_BPIX_18 (6 << 25)
-
struct imx_fb_videomode {
struct fb_videomode mode;
u32 pcr;
@@ -64,42 +56,50 @@ struct imx_fb_videomode {
#define LCDC_SSA 0x00
#define LCDC_SIZE 0x04
-#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
+#define SIZE_XMAX_MASK GENMASK(25, 20)
-#define YMAX_MASK_IMX1 0x1ff
-#define YMAX_MASK_IMX21 0x3ff
+#define YMAX_MASK_IMX1 GENMASK(8, 0)
+#define YMAX_MASK_IMX21 GENMASK(9, 0)
#define LCDC_VPW 0x08
-#define VPW_VPW(x) ((x) & 0x3ff)
+#define VPW_VPW_MASK GENMASK(9, 0)
#define LCDC_CPOS 0x0C
-#define CPOS_CC1 (1<<31)
-#define CPOS_CC0 (1<<30)
-#define CPOS_OP (1<<28)
-#define CPOS_CXP(x) (((x) & 3ff) << 16)
+#define CPOS_CC1 BIT(31)
+#define CPOS_CC0 BIT(30)
+#define CPOS_OP BIT(28)
+#define CPOS_CXP_MASK GENMASK(25, 16)
#define LCDC_LCWHB 0x10
-#define LCWHB_BK_EN (1<<31)
-#define LCWHB_CW(w) (((w) & 0x1f) << 24)
-#define LCWHB_CH(h) (((h) & 0x1f) << 16)
-#define LCWHB_BD(x) ((x) & 0xff)
+#define LCWHB_BK_EN BIT(31)
+#define LCWHB_CW_MASK GENMASK(28, 24)
+#define LCWHB_CH_MASK GENMASK(20, 16)
+#define LCWHB_BD_MASK GENMASK(7, 0)
#define LCDC_LCHCC 0x14
#define LCDC_PCR 0x18
+#define PCR_TFT BIT(31)
+#define PCR_COLOR BIT(30)
+#define PCR_BPIX_MASK GENMASK(27, 25)
+#define PCR_BPIX_8 3
+#define PCR_BPIX_12 4
+#define PCR_BPIX_16 5
+#define PCR_BPIX_18 6
+#define PCR_PCD_MASK GENMASK(5, 0)
#define LCDC_HCR 0x1C
-#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
-#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
-#define HCR_H_WAIT_2(x) ((x) & 0xff)
+#define HCR_H_WIDTH_MASK GENMASK(31, 26)
+#define HCR_H_WAIT_1_MASK GENMASK(15, 8)
+#define HCR_H_WAIT_2_MASK GENMASK(7, 0)
#define LCDC_VCR 0x20
-#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
-#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
-#define VCR_V_WAIT_2(x) ((x) & 0xff)
+#define VCR_V_WIDTH_MASK GENMASK(31, 26)
+#define VCR_V_WAIT_1_MASK GENMASK(15, 8)
+#define VCR_V_WAIT_2_MASK GENMASK(7, 0)
#define LCDC_POS 0x24
-#define POS_POS(x) ((x) & 1f)
+#define POS_POS_MASK GENMASK(4, 0)
#define LCDC_LSCR1 0x28
/* bit fields in imxfb.h */
@@ -112,24 +112,24 @@ struct imx_fb_videomode {
#define LCDC_RMCR 0x34
-#define RMCR_LCDC_EN_MX1 (1<<1)
+#define RMCR_LCDC_EN_MX1 BIT(1)
-#define RMCR_SELF_REF (1<<0)
+#define RMCR_SELF_REF BIT(0)
#define LCDC_LCDICR 0x38
-#define LCDICR_INT_SYN (1<<2)
-#define LCDICR_INT_CON (1)
+#define LCDICR_INT_SYN BIT(2)
+#define LCDICR_INT_CON BIT(0)
#define LCDC_LCDISR 0x40
-#define LCDISR_UDR_ERR (1<<3)
-#define LCDISR_ERR_RES (1<<2)
-#define LCDISR_EOF (1<<1)
-#define LCDISR_BOF (1<<0)
+#define LCDISR_UDR_ERR BIT(3)
+#define LCDISR_ERR_RES BIT(2)
+#define LCDISR_EOF BIT(1)
+#define LCDISR_BOF BIT(0)
#define IMXFB_LSCR1_DEFAULT 0x00120300
#define LCDC_LAUSCR 0x80
-#define LAUSCR_AUS_MODE (1<<31)
+#define LAUSCR_AUS_MODE BIT(31)
/* Used fb-mode. Can be set on kernel command line, therefore file-static. */
static const char *fb_mode;
@@ -150,6 +150,12 @@ enum imxfb_type {
IMX21_FB,
};
+enum imxfb_panel_type {
+ PANEL_TYPE_MONOCHROME,
+ PANEL_TYPE_CSTN,
+ PANEL_TYPE_TFT,
+};
+
struct imxfb_info {
struct platform_device *pdev;
void __iomem *regs;
@@ -157,6 +163,7 @@ struct imxfb_info {
struct clk *clk_ahb;
struct clk *clk_per;
enum imxfb_type devtype;
+ enum imxfb_panel_type panel_type;
bool enabled;
/*
@@ -273,10 +280,10 @@ static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
struct imxfb_info *fbi = info->par;
u_int val, ret = 1;
-#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
+#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
if (regno < fbi->palette_size) {
val = (CNVT_TOHW(red, 4) << 8) |
- (CNVT_TOHW(green,4) << 4) |
+ (CNVT_TOHW(green, 4) << 4) |
CNVT_TOHW(blue, 4);
writel(val, fbi->regs + 0x800 + (regno << 2));
@@ -405,23 +412,23 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
pcr = (unsigned int)tmp;
- if (--pcr > 0x3F) {
- pcr = 0x3F;
- printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
- lcd_clk / pcr);
+ if (--pcr > PCR_PCD_MASK) {
+ pcr = PCR_PCD_MASK;
+ dev_warn(&fbi->pdev->dev, "Must limit pixel clock to %luHz\n",
+ lcd_clk / pcr);
}
switch (var->bits_per_pixel) {
case 32:
- pcr |= PCR_BPIX_18;
+ pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_18);
rgb = &def_rgb_18;
break;
case 16:
default:
if (is_imx1_fb(fbi))
- pcr |= PCR_BPIX_12;
+ pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_12);
else
- pcr |= PCR_BPIX_16;
+ pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_16);
if (imxfb_mode->pcr & PCR_TFT)
rgb = &def_rgb_16_tft;
@@ -429,13 +436,13 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
rgb = &def_rgb_16_stn;
break;
case 8:
- pcr |= PCR_BPIX_8;
+ pcr |= FIELD_PREP(PCR_BPIX_MASK, PCR_BPIX_8);
rgb = &def_rgb_8;
break;
}
/* add sync polarities */
- pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
+ pcr |= imxfb_mode->pcr & ~(PCR_PCD_MASK | PCR_BPIX_MASK);
fbi->pcr = pcr;
/*
@@ -444,6 +451,13 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode)
fbi->lauscr = LAUSCR_AUS_MODE;
+ if (imxfb_mode->pcr & PCR_TFT)
+ fbi->panel_type = PANEL_TYPE_TFT;
+ else if (imxfb_mode->pcr & PCR_COLOR)
+ fbi->panel_type = PANEL_TYPE_CSTN;
+ else
+ fbi->panel_type = PANEL_TYPE_MONOCHROME;
+
/*
* Copy the RGB parameters for this display
* from the machine specific parameters.
@@ -506,7 +520,7 @@ static int imxfb_enable_controller(struct imxfb_info *fbi)
writel(fbi->map_dma, fbi->regs + LCDC_SSA);
/* panning offset 0 (0 pixel offset) */
- writel(0x00000000, fbi->regs + LCDC_POS);
+ writel(FIELD_PREP(POS_POS_MASK, 0), fbi->regs + LCDC_POS);
/* disable hardware cursor */
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
@@ -562,7 +576,7 @@ static int imxfb_blank(int blank, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
- pr_debug("imxfb_blank: blank=%d\n", blank);
+ pr_debug("%s: blank=%d\n", __func__, blank);
switch (blank) {
case FB_BLANK_POWERDOWN:
@@ -596,6 +610,7 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
{
struct imxfb_info *fbi = info->par;
u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21;
+ u8 left_margin_low;
pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
var->xres, var->hsync_len,
@@ -604,49 +619,59 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
var->yres, var->vsync_len,
var->upper_margin, var->lower_margin);
+ if (fbi->panel_type == PANEL_TYPE_TFT)
+ left_margin_low = 3;
+ else if (fbi->panel_type == PANEL_TYPE_CSTN)
+ left_margin_low = 2;
+ else
+ left_margin_low = 0;
+
#if DEBUG_VAR
if (var->xres < 16 || var->xres > 1024)
- printk(KERN_ERR "%s: invalid xres %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid xres %d\n",
info->fix.id, var->xres);
if (var->hsync_len < 1 || var->hsync_len > 64)
- printk(KERN_ERR "%s: invalid hsync_len %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid hsync_len %d\n",
info->fix.id, var->hsync_len);
- if (var->left_margin < 3 || var->left_margin > 255)
- printk(KERN_ERR "%s: invalid left_margin %d\n",
+ if (var->left_margin < left_margin_low || var->left_margin > 255)
+ dev_err(&fbi->pdev->dev, "%s: invalid left_margin %d\n",
info->fix.id, var->left_margin);
if (var->right_margin < 1 || var->right_margin > 255)
- printk(KERN_ERR "%s: invalid right_margin %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid right_margin %d\n",
info->fix.id, var->right_margin);
if (var->yres < 1 || var->yres > ymax_mask)
- printk(KERN_ERR "%s: invalid yres %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid yres %d\n",
info->fix.id, var->yres);
if (var->vsync_len > 100)
- printk(KERN_ERR "%s: invalid vsync_len %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid vsync_len %d\n",
info->fix.id, var->vsync_len);
if (var->upper_margin > 63)
- printk(KERN_ERR "%s: invalid upper_margin %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid upper_margin %d\n",
info->fix.id, var->upper_margin);
if (var->lower_margin > 255)
- printk(KERN_ERR "%s: invalid lower_margin %d\n",
+ dev_err(&fbi->pdev->dev, "%s: invalid lower_margin %d\n",
info->fix.id, var->lower_margin);
#endif
/* physical screen start address */
- writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
- fbi->regs + LCDC_VPW);
+ writel(FIELD_PREP(VPW_VPW_MASK,
+ var->xres * var->bits_per_pixel / 8 / 4),
+ fbi->regs + LCDC_VPW);
- writel(HCR_H_WIDTH(var->hsync_len - 1) |
- HCR_H_WAIT_1(var->right_margin - 1) |
- HCR_H_WAIT_2(var->left_margin - 3),
- fbi->regs + LCDC_HCR);
+ writel(FIELD_PREP(HCR_H_WIDTH_MASK, var->hsync_len - 1) |
+ FIELD_PREP(HCR_H_WAIT_1_MASK, var->right_margin - 1) |
+ FIELD_PREP(HCR_H_WAIT_2_MASK,
+ var->left_margin - left_margin_low),
+ fbi->regs + LCDC_HCR);
- writel(VCR_V_WIDTH(var->vsync_len) |
- VCR_V_WAIT_1(var->lower_margin) |
- VCR_V_WAIT_2(var->upper_margin),
- fbi->regs + LCDC_VCR);
+ writel(FIELD_PREP(VCR_V_WIDTH_MASK, var->vsync_len) |
+ FIELD_PREP(VCR_V_WAIT_1_MASK, var->lower_margin) |
+ FIELD_PREP(VCR_V_WAIT_2_MASK, var->upper_margin),
+ fbi->regs + LCDC_VCR);
- writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask),
- fbi->regs + LCDC_SIZE);
+ writel(FIELD_PREP(SIZE_XMAX_MASK, var->xres >> 4) |
+ (var->yres & ymax_mask),
+ fbi->regs + LCDC_SIZE);
writel(fbi->pcr, fbi->regs + LCDC_PCR);
if (fbi->pwmr)
@@ -669,8 +694,6 @@ static int imxfb_init_fbinfo(struct platform_device *pdev)
struct imxfb_info *fbi = info->par;
struct device_node *np;
- pr_debug("%s\n",__func__);
-
info->pseudo_palette = devm_kmalloc_array(&pdev->dev, 16,
sizeof(u32), GFP_KERNEL);
if (!info->pseudo_palette)
@@ -678,6 +701,7 @@ static int imxfb_init_fbinfo(struct platform_device *pdev)
memset(fbi, 0, sizeof(struct imxfb_info));
+ fbi->pdev = pdev;
fbi->devtype = pdev->id_entry->driver_data;
strscpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
@@ -922,8 +946,10 @@ static int imxfb_probe(struct platform_device *pdev)
if (ret)
goto failed_init;
- /* Calculate maximum bytes used per pixel. In most cases this should
- * be the same as m->bpp/8 */
+ /*
+ * Calculate maximum bytes used per pixel. In most cases this should
+ * be the same as m->bpp/8
+ */
m = &fbi->mode[0];
bytes_per_pixel = (m->bpp + 7) / 8;
for (i = 0; i < fbi->num_modes; i++, m++)
@@ -1021,7 +1047,6 @@ static int imxfb_probe(struct platform_device *pdev)
lcd->props.max_contrast = 0xff;
imxfb_enable_controller(fbi);
- fbi->pdev = pdev;
return 0;
diff --git a/drivers/video/fbdev/intelfb/Makefile b/drivers/video/fbdev/intelfb/Makefile
deleted file mode 100644
index 7ff2debb31af..000000000000
--- a/drivers/video/fbdev/intelfb/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_FB_INTEL) += intelfb.o
-
-intelfb-y := intelfbdrv.o intelfbhw.o
-intelfb-$(CONFIG_FB_INTEL_I2C) += intelfb_i2c.o
-intelfb-objs := $(intelfb-y)
-
-ccflags-$(CONFIG_FB_INTEL_DEBUG) := -DDEBUG -DREGDUMP
diff --git a/drivers/video/fbdev/intelfb/intelfb.h b/drivers/video/fbdev/intelfb/intelfb.h
deleted file mode 100644
index 5de703902a21..000000000000
--- a/drivers/video/fbdev/intelfb/intelfb.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _INTELFB_H
-#define _INTELFB_H
-
-/* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */
-
-#include <linux/agp_backend.h>
-#include <linux/fb.h>
-
-#ifdef CONFIG_FB_INTEL_I2C
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
-#endif
-
-/*** Version/name ***/
-#define INTELFB_VERSION "0.9.6"
-#define INTELFB_MODULE_NAME "intelfb"
-#define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM"
-
-
-/*** Debug/feature defines ***/
-
-#ifndef DEBUG
-#define DEBUG 0
-#endif
-
-#ifndef VERBOSE
-#define VERBOSE 0
-#endif
-
-#ifndef REGDUMP
-#define REGDUMP 0
-#endif
-
-#ifndef DETECT_VGA_CLASS_ONLY
-#define DETECT_VGA_CLASS_ONLY 1
-#endif
-
-#ifndef ALLOCATE_FOR_PANNING
-#define ALLOCATE_FOR_PANNING 1
-#endif
-
-#ifndef PREFERRED_MODE
-#define PREFERRED_MODE "1024x768-32@70"
-#endif
-
-/*** hw-related values ***/
-
-/* Resource Allocation */
-#define INTELFB_FB_ACQUIRED 1
-#define INTELFB_MMIO_ACQUIRED 2
-
-/* PCI ids for supported devices */
-#define PCI_DEVICE_ID_INTEL_830M 0x3577
-#define PCI_DEVICE_ID_INTEL_845G 0x2562
-#define PCI_DEVICE_ID_INTEL_85XGM 0x3582
-#define PCI_DEVICE_ID_INTEL_854 0x358E
-#define PCI_DEVICE_ID_INTEL_865G 0x2572
-#define PCI_DEVICE_ID_INTEL_915G 0x2582
-#define PCI_DEVICE_ID_INTEL_915GM 0x2592
-#define PCI_DEVICE_ID_INTEL_945G 0x2772
-#define PCI_DEVICE_ID_INTEL_945GM 0x27A2
-#define PCI_DEVICE_ID_INTEL_945GME 0x27AE
-#define PCI_DEVICE_ID_INTEL_965G 0x29A2
-#define PCI_DEVICE_ID_INTEL_965GM 0x2A02
-
-/* Size of MMIO region */
-#define INTEL_REG_SIZE 0x80000
-
-#define STRIDE_ALIGNMENT 16
-#define STRIDE_ALIGNMENT_I9XX 64
-
-#define PALETTE_8_ENTRIES 256
-
-
-/*** Macros ***/
-
-/* basic arithmetic */
-#define KB(x) ((x) * 1024)
-#define MB(x) ((x) * 1024 * 1024)
-#define BtoKB(x) ((x) / 1024)
-#define BtoMB(x) ((x) / 1024 / 1024)
-
-#define GTT_PAGE_SIZE KB(4)
-
-#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
-#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
-#define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE)
-#define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE)
-
-/* messages */
-#define PFX INTELFB_MODULE_NAME ": "
-
-#define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args)
-#define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args)
-#define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args)
-#define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args)
-#if DEBUG
-#define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args)
-#else
-#define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args)
-#endif
-
-/* get commonly used pointers */
-#define GET_DINFO(info) (info)->par
-
-/* misc macros */
-#define ACCEL(d, i) \
- ((d)->accel && !(d)->ring_lockup && \
- ((i)->var.accel_flags & FB_ACCELF_TEXT))
-
-/*#define NOACCEL_CHIPSET(d) \
- ((d)->chipset != INTEL_865G)*/
-#define NOACCEL_CHIPSET(d) \
- (0)
-
-#define FIXED_MODE(d) ((d)->fixed_mode)
-
-/*** Driver parameters ***/
-
-#define RINGBUFFER_SIZE KB(64)
-#define HW_CURSOR_SIZE KB(4)
-
-/* Intel agpgart driver */
-#define AGP_PHYSICAL_MEMORY 2
-
-/* store information about an Ixxx DVO */
-/* The i830->i865 use multiple DVOs with multiple i2cs */
-/* the i915, i945 have a single sDVO i2c bus - which is different */
-#define MAX_OUTPUTS 6
-
-/* these are outputs from the chip - integrated only
- external chips are via DVO or SDVO output */
-#define INTELFB_OUTPUT_UNUSED 0
-#define INTELFB_OUTPUT_ANALOG 1
-#define INTELFB_OUTPUT_DVO 2
-#define INTELFB_OUTPUT_SDVO 3
-#define INTELFB_OUTPUT_LVDS 4
-#define INTELFB_OUTPUT_TVOUT 5
-
-#define INTELFB_DVO_CHIP_NONE 0
-#define INTELFB_DVO_CHIP_LVDS 1
-#define INTELFB_DVO_CHIP_TMDS 2
-#define INTELFB_DVO_CHIP_TVOUT 4
-
-#define INTELFB_OUTPUT_PIPE_NC 0
-#define INTELFB_OUTPUT_PIPE_A 1
-#define INTELFB_OUTPUT_PIPE_B 2
-
-/*** Data Types ***/
-
-/* supported chipsets */
-enum intel_chips {
- INTEL_830M,
- INTEL_845G,
- INTEL_85XGM,
- INTEL_852GM,
- INTEL_852GME,
- INTEL_854,
- INTEL_855GM,
- INTEL_855GME,
- INTEL_865G,
- INTEL_915G,
- INTEL_915GM,
- INTEL_945G,
- INTEL_945GM,
- INTEL_945GME,
- INTEL_965G,
- INTEL_965GM,
-};
-
-struct intelfb_hwstate {
- u32 vga0_divisor;
- u32 vga1_divisor;
- u32 vga_pd;
- u32 dpll_a;
- u32 dpll_b;
- u32 fpa0;
- u32 fpa1;
- u32 fpb0;
- u32 fpb1;
- u32 palette_a[PALETTE_8_ENTRIES];
- u32 palette_b[PALETTE_8_ENTRIES];
- u32 htotal_a;
- u32 hblank_a;
- u32 hsync_a;
- u32 vtotal_a;
- u32 vblank_a;
- u32 vsync_a;
- u32 src_size_a;
- u32 bclrpat_a;
- u32 htotal_b;
- u32 hblank_b;
- u32 hsync_b;
- u32 vtotal_b;
- u32 vblank_b;
- u32 vsync_b;
- u32 src_size_b;
- u32 bclrpat_b;
- u32 adpa;
- u32 dvoa;
- u32 dvob;
- u32 dvoc;
- u32 dvoa_srcdim;
- u32 dvob_srcdim;
- u32 dvoc_srcdim;
- u32 lvds;
- u32 pipe_a_conf;
- u32 pipe_b_conf;
- u32 disp_arb;
- u32 cursor_a_control;
- u32 cursor_b_control;
- u32 cursor_a_base;
- u32 cursor_b_base;
- u32 cursor_size;
- u32 disp_a_ctrl;
- u32 disp_b_ctrl;
- u32 disp_a_base;
- u32 disp_b_base;
- u32 cursor_a_palette[4];
- u32 cursor_b_palette[4];
- u32 disp_a_stride;
- u32 disp_b_stride;
- u32 vgacntrl;
- u32 add_id;
- u32 swf0x[7];
- u32 swf1x[7];
- u32 swf3x[3];
- u32 fence[8];
- u32 instpm;
- u32 mem_mode;
- u32 fw_blc_0;
- u32 fw_blc_1;
- u16 hwstam;
- u16 ier;
- u16 iir;
- u16 imr;
-};
-
-struct intelfb_heap_data {
- u32 physical;
- u8 __iomem *virtual;
- u32 offset; /* in GATT pages */
- u32 size; /* in bytes */
-};
-
-#ifdef CONFIG_FB_INTEL_I2C
-struct intelfb_i2c_chan {
- struct intelfb_info *dinfo;
- u32 reg;
- struct i2c_adapter adapter;
- struct i2c_algo_bit_data algo;
-};
-#endif
-
-struct intelfb_output_rec {
- int type;
- int pipe;
- int flags;
-
-#ifdef CONFIG_FB_INTEL_I2C
- struct intelfb_i2c_chan i2c_bus;
- struct intelfb_i2c_chan ddc_bus;
-#endif
-};
-
-struct intelfb_vsync {
- wait_queue_head_t wait;
- unsigned int count;
- int pan_display;
- u32 pan_offset;
-};
-
-struct intelfb_info {
- struct fb_info *info;
- const struct fb_ops *fbops;
- struct pci_dev *pdev;
-
- struct intelfb_hwstate save_state;
-
- /* agpgart structs */
- struct agp_memory *gtt_fb_mem; /* use all stolen memory or vram */
- struct agp_memory *gtt_ring_mem; /* ring buffer */
- struct agp_memory *gtt_cursor_mem; /* hw cursor */
-
- /* use a gart reserved fb mem */
- u8 fbmem_gart;
-
- int wc_cookie;
-
- /* heap data */
- struct intelfb_heap_data aperture;
- struct intelfb_heap_data fb;
- struct intelfb_heap_data ring;
- struct intelfb_heap_data cursor;
-
- /* mmio regs */
- u32 mmio_base_phys;
- u8 __iomem *mmio_base;
-
- /* fb start offset (in bytes) */
- u32 fb_start;
-
- /* ring buffer */
- u32 ring_head;
- u32 ring_tail;
- u32 ring_tail_mask;
- u32 ring_space;
- u32 ring_lockup;
-
- /* palette */
- u32 pseudo_palette[16];
-
- /* chip info */
- int pci_chipset;
- int chipset;
- const char *name;
- int mobile;
-
- /* current mode */
- int bpp, depth;
- u32 visual;
- int xres, yres, pitch;
- int pixclock;
-
- /* current pipe */
- int pipe;
-
- /* some flags */
- int accel;
- int hwcursor;
- int fixed_mode;
- int ring_active;
- int flag;
- unsigned long irq_flags;
- int open;
-
- /* vsync */
- struct intelfb_vsync vsync;
- spinlock_t int_lock;
-
- /* hw cursor */
- int cursor_on;
- int cursor_blanked;
- u8 cursor_src[64];
-
- /* initial parameters */
- int initial_vga;
- struct fb_var_screeninfo initial_var;
- u32 initial_fb_base;
- u32 initial_video_ram;
- u32 initial_pitch;
-
- /* driver registered */
- int registered;
-
- /* index into plls */
- int pll_index;
-
- /* outputs */
- int num_outputs;
- struct intelfb_output_rec output[MAX_OUTPUTS];
-};
-
-#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) || \
- ((dinfo)->chipset == INTEL_915GM) || \
- ((dinfo)->chipset == INTEL_945G) || \
- ((dinfo)->chipset == INTEL_945GM) || \
- ((dinfo)->chipset == INTEL_945GME) || \
- ((dinfo)->chipset == INTEL_965G) || \
- ((dinfo)->chipset == INTEL_965GM))
-
-/*** function prototypes ***/
-
-extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
-
-#ifdef CONFIG_FB_INTEL_I2C
-extern void intelfb_create_i2c_busses(struct intelfb_info *dinfo);
-extern void intelfb_delete_i2c_busses(struct intelfb_info *dinfo);
-#endif
-
-#endif /* _INTELFB_H */
diff --git a/drivers/video/fbdev/intelfb/intelfb_i2c.c b/drivers/video/fbdev/intelfb/intelfb_i2c.c
deleted file mode 100644
index 3300bd31d9d7..000000000000
--- a/drivers/video/fbdev/intelfb/intelfb_i2c.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/**************************************************************************
-
- Copyright 2006 Dave Airlie <airlied@linux.ie>
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/pci.h>
-#include <linux/fb.h>
-
-#include <linux/i2c.h>
-#include <linux/i2c-algo-bit.h>
-
-#include <asm/io.h>
-
-#include "intelfb.h"
-#include "intelfbhw.h"
-
-/* bit locations in the registers */
-#define SCL_DIR_MASK 0x0001
-#define SCL_DIR 0x0002
-#define SCL_VAL_MASK 0x0004
-#define SCL_VAL_OUT 0x0008
-#define SCL_VAL_IN 0x0010
-#define SDA_DIR_MASK 0x0100
-#define SDA_DIR 0x0200
-#define SDA_VAL_MASK 0x0400
-#define SDA_VAL_OUT 0x0800
-#define SDA_VAL_IN 0x1000
-
-static void intelfb_gpio_setscl(void *data, int state)
-{
- struct intelfb_i2c_chan *chan = data;
- struct intelfb_info *dinfo = chan->dinfo;
- u32 val;
-
- OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) |
- SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
- val = INREG(chan->reg);
-}
-
-static void intelfb_gpio_setsda(void *data, int state)
-{
- struct intelfb_i2c_chan *chan = data;
- struct intelfb_info *dinfo = chan->dinfo;
- u32 val;
-
- OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) |
- SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
- val = INREG(chan->reg);
-}
-
-static int intelfb_gpio_getscl(void *data)
-{
- struct intelfb_i2c_chan *chan = data;
- struct intelfb_info *dinfo = chan->dinfo;
- u32 val;
-
- OUTREG(chan->reg, SCL_DIR_MASK);
- OUTREG(chan->reg, 0);
- val = INREG(chan->reg);
- return ((val & SCL_VAL_IN) != 0);
-}
-
-static int intelfb_gpio_getsda(void *data)
-{
- struct intelfb_i2c_chan *chan = data;
- struct intelfb_info *dinfo = chan->dinfo;
- u32 val;
-
- OUTREG(chan->reg, SDA_DIR_MASK);
- OUTREG(chan->reg, 0);
- val = INREG(chan->reg);
- return ((val & SDA_VAL_IN) != 0);
-}
-
-static int intelfb_setup_i2c_bus(struct intelfb_info *dinfo,
- struct intelfb_i2c_chan *chan,
- const u32 reg, const char *name,
- int class)
-{
- int rc;
-
- chan->dinfo = dinfo;
- chan->reg = reg;
- snprintf(chan->adapter.name, sizeof(chan->adapter.name),
- "intelfb %s", name);
- chan->adapter.class = class;
- chan->adapter.owner = THIS_MODULE;
- chan->adapter.algo_data = &chan->algo;
- chan->adapter.dev.parent = &chan->dinfo->pdev->dev;
- chan->algo.setsda = intelfb_gpio_setsda;
- chan->algo.setscl = intelfb_gpio_setscl;
- chan->algo.getsda = intelfb_gpio_getsda;
- chan->algo.getscl = intelfb_gpio_getscl;
- chan->algo.udelay = 40;
- chan->algo.timeout = 20;
- chan->algo.data = chan;
-
- i2c_set_adapdata(&chan->adapter, chan);
-
- /* Raise SCL and SDA */
- intelfb_gpio_setsda(chan, 1);
- intelfb_gpio_setscl(chan, 1);
- udelay(20);
-
- rc = i2c_bit_add_bus(&chan->adapter);
- if (rc == 0)
- DBG_MSG("I2C bus %s registered.\n", name);
- else
- WRN_MSG("Failed to register I2C bus %s.\n", name);
- return rc;
-}
-
-void intelfb_create_i2c_busses(struct intelfb_info *dinfo)
-{
- int i = 0;
-
- /* everyone has at least a single analog output */
- dinfo->num_outputs = 1;
- dinfo->output[i].type = INTELFB_OUTPUT_ANALOG;
-
- /* setup the DDC bus for analog output */
- intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus, GPIOA,
- "CRTDDC_A", I2C_CLASS_DDC);
- i++;
-
- /* need to add the output busses for each device
- - this function is very incomplete
- - i915GM has LVDS and TVOUT for example
- */
- switch(dinfo->chipset) {
- case INTEL_830M:
- case INTEL_845G:
- case INTEL_854:
- case INTEL_855GM:
- case INTEL_865G:
- dinfo->output[i].type = INTELFB_OUTPUT_DVO;
- intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus,
- GPIOD, "DVODDC_D", I2C_CLASS_DDC);
- intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus,
- GPIOE, "DVOI2C_E", 0);
- i++;
- break;
- case INTEL_915G:
- case INTEL_915GM:
- /* has some LVDS + tv-out */
- case INTEL_945G:
- case INTEL_945GM:
- case INTEL_945GME:
- case INTEL_965G:
- case INTEL_965GM:
- /* SDVO ports have a single control bus - 2 devices */
- dinfo->output[i].type = INTELFB_OUTPUT_SDVO;
- intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus,
- GPIOE, "SDVOCTRL_E", 0);
- /* TODO: initialize the SDVO */
- /* I830SDVOInit(pScrn, i, DVOB); */
- i++;
-
- /* set up SDVOC */
- dinfo->output[i].type = INTELFB_OUTPUT_SDVO;
- dinfo->output[i].i2c_bus = dinfo->output[i - 1].i2c_bus;
- /* TODO: initialize the SDVO */
- /* I830SDVOInit(pScrn, i, DVOC); */
- i++;
- break;
- }
- dinfo->num_outputs = i;
-}
-
-void intelfb_delete_i2c_busses(struct intelfb_info *dinfo)
-{
- int i;
-
- for (i = 0; i < MAX_OUTPUTS; i++) {
- if (dinfo->output[i].i2c_bus.dinfo) {
- i2c_del_adapter(&dinfo->output[i].i2c_bus.adapter);
- dinfo->output[i].i2c_bus.dinfo = NULL;
- }
- if (dinfo->output[i].ddc_bus.dinfo) {
- i2c_del_adapter(&dinfo->output[i].ddc_bus.adapter);
- dinfo->output[i].ddc_bus.dinfo = NULL;
- }
- }
-}
diff --git a/drivers/video/fbdev/intelfb/intelfbdrv.c b/drivers/video/fbdev/intelfb/intelfbdrv.c
deleted file mode 100644
index d29d80a16295..000000000000
--- a/drivers/video/fbdev/intelfb/intelfbdrv.c
+++ /dev/null
@@ -1,1680 +0,0 @@
-/*
- * intelfb
- *
- * Linux framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G/915G/915GM/
- * 945G/945GM/945GME/965G/965GM integrated graphics chips.
- *
- * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
- * 2004 Sylvain Meyer
- * 2006 David Airlie
- *
- * This driver consists of two parts. The first part (intelfbdrv.c) provides
- * the basic fbdev interfaces, is derived in part from the radeonfb and
- * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
- * provides the code to program the hardware. Most of it is derived from
- * the i810/i830 XFree86 driver. The HW-specific code is covered here
- * under a dual license (GPL and MIT/XFree86 license).
- *
- * Author: David Dawes
- *
- */
-
-/* $DHD: intelfb/intelfbdrv.c,v 1.20 2003/06/27 15:17:40 dawes Exp $ */
-
-/*
- * Changes:
- * 01/2003 - Initial driver (0.1.0), no mode switching, no acceleration.
- * This initial version is a basic core that works a lot like
- * the vesafb driver. It must be built-in to the kernel,
- * and the initial video mode must be set with vga=XXX at
- * boot time. (David Dawes)
- *
- * 01/2003 - Version 0.2.0: Mode switching added, colormap support
- * implemented, Y panning, and soft screen blanking implemented.
- * No acceleration yet. (David Dawes)
- *
- * 01/2003 - Version 0.3.0: fbcon acceleration support added. Module
- * option handling added. (David Dawes)
- *
- * 01/2003 - Version 0.4.0: fbcon HW cursor support added. (David Dawes)
- *
- * 01/2003 - Version 0.4.1: Add auto-generation of built-in modes.
- * (David Dawes)
- *
- * 02/2003 - Version 0.4.2: Add check for active non-CRT devices, and
- * mode validation checks. (David Dawes)
- *
- * 02/2003 - Version 0.4.3: Check when the VC is in graphics mode so that
- * acceleration is disabled while an XFree86 server is running.
- * (David Dawes)
- *
- * 02/2003 - Version 0.4.4: Monitor DPMS support. (David Dawes)
- *
- * 02/2003 - Version 0.4.5: Basic XFree86 + fbdev working. (David Dawes)
- *
- * 02/2003 - Version 0.5.0: Modify to work with the 2.5.32 kernel as well
- * as 2.4.x kernels. (David Dawes)
- *
- * 02/2003 - Version 0.6.0: Split out HW-specifics into a separate file.
- * (David Dawes)
- *
- * 02/2003 - Version 0.7.0: Test on 852GM/855GM. Acceleration and HW
- * cursor are disabled on this platform. (David Dawes)
- *
- * 02/2003 - Version 0.7.1: Test on 845G. Acceleration is disabled
- * on this platform. (David Dawes)
- *
- * 02/2003 - Version 0.7.2: Test on 830M. Acceleration and HW
- * cursor are disabled on this platform. (David Dawes)
- *
- * 02/2003 - Version 0.7.3: Fix 8-bit modes for mobile platforms
- * (David Dawes)
- *
- * 02/2003 - Version 0.7.4: Add checks for FB and FBCON_HAS_CFB* configured
- * in the kernel, and add mode bpp verification and default
- * bpp selection based on which FBCON_HAS_CFB* are configured.
- * (David Dawes)
- *
- * 02/2003 - Version 0.7.5: Add basic package/install scripts based on the
- * DRI packaging scripts. (David Dawes)
- *
- * 04/2003 - Version 0.7.6: Fix typo that affects builds with SMP-enabled
- * kernels. (David Dawes, reported by Anupam).
- *
- * 06/2003 - Version 0.7.7:
- * Fix Makefile.kernel build problem (Tsutomu Yasuda).
- * Fix mis-placed #endif (2.4.21 kernel).
- *
- * 09/2004 - Version 0.9.0 - by Sylvain Meyer
- * Port to linux 2.6 kernel fbdev
- * Fix HW accel and HW cursor on i845G
- * Use of agpgart for fb memory reservation
- * Add mtrr support
- *
- * 10/2004 - Version 0.9.1
- * Use module_param instead of old MODULE_PARM
- * Some cleanup
- *
- * 11/2004 - Version 0.9.2
- * Add vram option to reserve more memory than stolen by BIOS
- * Fix intelfbhw_pan_display typo
- * Add __initdata annotations
- *
- * 04/2008 - Version 0.9.5
- * Add support for 965G/965GM. (Maik Broemme <mbroemme@plusserver.de>)
- *
- * 08/2008 - Version 0.9.6
- * Add support for 945GME. (Phil Endecott <spam_from_intelfb@chezphil.org>)
- */
-
-#include <linux/aperture.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/vmalloc.h>
-#include <linux/pagemap.h>
-#include <linux/screen_info.h>
-
-#include <asm/io.h>
-
-#include "intelfb.h"
-#include "intelfbhw.h"
-#include "../edid.h"
-
-static void get_initial_mode(struct intelfb_info *dinfo);
-static void update_dinfo(struct intelfb_info *dinfo,
- struct fb_var_screeninfo *var);
-static int intelfb_open(struct fb_info *info, int user);
-static int intelfb_release(struct fb_info *info, int user);
-static int intelfb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info);
-static int intelfb_set_par(struct fb_info *info);
-static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info);
-
-static int intelfb_blank(int blank, struct fb_info *info);
-static int intelfb_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info);
-
-static void intelfb_fillrect(struct fb_info *info,
- const struct fb_fillrect *rect);
-static void intelfb_copyarea(struct fb_info *info,
- const struct fb_copyarea *region);
-static void intelfb_imageblit(struct fb_info *info,
- const struct fb_image *image);
-static int intelfb_cursor(struct fb_info *info,
- struct fb_cursor *cursor);
-
-static int intelfb_sync(struct fb_info *info);
-
-static int intelfb_ioctl(struct fb_info *info,
- unsigned int cmd, unsigned long arg);
-
-static int intelfb_pci_register(struct pci_dev *pdev,
- const struct pci_device_id *ent);
-static void intelfb_pci_unregister(struct pci_dev *pdev);
-static int intelfb_set_fbinfo(struct intelfb_info *dinfo);
-
-/*
- * Limiting the class to PCI_CLASS_DISPLAY_VGA prevents function 1 of the
- * mobile chipsets from being registered.
- */
-#if DETECT_VGA_CLASS_ONLY
-#define INTELFB_CLASS_MASK ~0 << 8
-#else
-#define INTELFB_CLASS_MASK 0
-#endif
-
-static const struct pci_device_id intelfb_pci_table[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_830M, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_830M },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_845G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_845G },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_85XGM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_85XGM },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_865G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_865G },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_854, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_854 },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915G },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915GM },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945G },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945GM },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945GME, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945GME },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_965G },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_965GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_965GM },
- { 0, }
-};
-
-/* Global data */
-static int num_registered = 0;
-
-/* fb ops */
-static const struct fb_ops intel_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = intelfb_open,
- .fb_release = intelfb_release,
- __FB_DEFAULT_IOMEM_OPS_RDWR,
- .fb_check_var = intelfb_check_var,
- .fb_set_par = intelfb_set_par,
- .fb_setcolreg = intelfb_setcolreg,
- .fb_blank = intelfb_blank,
- .fb_pan_display = intelfb_pan_display,
- .fb_fillrect = intelfb_fillrect,
- .fb_copyarea = intelfb_copyarea,
- .fb_imageblit = intelfb_imageblit,
- .fb_cursor = intelfb_cursor,
- .fb_sync = intelfb_sync,
- .fb_ioctl = intelfb_ioctl,
- __FB_DEFAULT_IOMEM_OPS_MMAP,
-};
-
-/* PCI driver module table */
-static struct pci_driver intelfb_driver = {
- .name = "intelfb",
- .id_table = intelfb_pci_table,
- .probe = intelfb_pci_register,
- .remove = intelfb_pci_unregister,
-};
-
-/* Module description/parameters */
-MODULE_AUTHOR("David Dawes <dawes@tungstengraphics.com>, "
- "Sylvain Meyer <sylvain.meyer@worldonline.fr>");
-MODULE_DESCRIPTION("Framebuffer driver for Intel(R) " SUPPORTED_CHIPSETS
- " chipsets");
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DEVICE_TABLE(pci, intelfb_pci_table);
-
-static bool accel = 1;
-static int vram = 4;
-static bool hwcursor = 0;
-static bool mtrr = 1;
-static bool fixed = 0;
-static bool noinit = 0;
-static bool noregister = 0;
-static bool probeonly = 0;
-static bool idonly = 0;
-static int bailearly = 0;
-static int voffset = 48;
-static char *mode = NULL;
-
-module_param(accel, bool, S_IRUGO);
-MODULE_PARM_DESC(accel, "Enable hardware acceleration");
-module_param(vram, int, S_IRUGO);
-MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB");
-module_param(voffset, int, S_IRUGO);
-MODULE_PARM_DESC(voffset, "Offset of framebuffer in MiB");
-module_param(hwcursor, bool, S_IRUGO);
-MODULE_PARM_DESC(hwcursor, "Enable HW cursor");
-module_param(mtrr, bool, S_IRUGO);
-MODULE_PARM_DESC(mtrr, "Enable MTRR support");
-module_param(fixed, bool, S_IRUGO);
-MODULE_PARM_DESC(fixed, "Disable mode switching");
-module_param(noinit, bool, 0);
-MODULE_PARM_DESC(noinit, "Don't initialise graphics mode when loading");
-module_param(noregister, bool, 0);
-MODULE_PARM_DESC(noregister, "Don't register, just probe and exit (debug)");
-module_param(probeonly, bool, 0);
-MODULE_PARM_DESC(probeonly, "Do a minimal probe (debug)");
-module_param(idonly, bool, 0);
-MODULE_PARM_DESC(idonly, "Just identify without doing anything else (debug)");
-module_param(bailearly, int, 0);
-MODULE_PARM_DESC(bailearly, "Bail out early, depending on value (debug)");
-module_param(mode, charp, S_IRUGO);
-MODULE_PARM_DESC(mode,
- "Initial video mode \"<xres>x<yres>[-<depth>][@<refresh>]\"");
-
-#ifndef MODULE
-#define OPT_EQUAL(opt, name) (!strncmp(opt, name, strlen(name)))
-#define OPT_INTVAL(opt, name) simple_strtoul(opt + strlen(name) + 1, NULL, 0)
-#define OPT_STRVAL(opt, name) (opt + strlen(name))
-
-static __inline__ char * get_opt_string(const char *this_opt, const char *name)
-{
- const char *p;
- int i;
- char *ret;
-
- p = OPT_STRVAL(this_opt, name);
- i = 0;
- while (p[i] && p[i] != ' ' && p[i] != ',')
- i++;
- ret = kmalloc(i + 1, GFP_KERNEL);
- if (ret) {
- strncpy(ret, p, i);
- ret[i] = '\0';
- }
- return ret;
-}
-
-static __inline__ int get_opt_int(const char *this_opt, const char *name,
- int *ret)
-{
- if (!ret)
- return 0;
-
- if (!OPT_EQUAL(this_opt, name))
- return 0;
-
- *ret = OPT_INTVAL(this_opt, name);
- return 1;
-}
-
-static __inline__ int get_opt_bool(const char *this_opt, const char *name,
- bool *ret)
-{
- if (!ret)
- return 0;
-
- if (OPT_EQUAL(this_opt, name)) {
- if (this_opt[strlen(name)] == '=')
- *ret = simple_strtoul(this_opt + strlen(name) + 1,
- NULL, 0);
- else
- *ret = 1;
- } else {
- if (OPT_EQUAL(this_opt, "no") && OPT_EQUAL(this_opt + 2, name))
- *ret = 0;
- else
- return 0;
- }
- return 1;
-}
-
-static int __init intelfb_setup(char *options)
-{
- char *this_opt;
-
- DBG_MSG("intelfb_setup\n");
-
- if (!options || !*options) {
- DBG_MSG("no options\n");
- return 0;
- } else
- DBG_MSG("options: %s\n", options);
-
- /*
- * These are the built-in options analogous to the module parameters
- * defined above.
- *
- * The syntax is:
- *
- * video=intelfb:[mode][,<param>=<val>] ...
- *
- * e.g.,
- *
- * video=intelfb:1024x768-16@75,accel=0
- */
-
- while ((this_opt = strsep(&options, ","))) {
- if (!*this_opt)
- continue;
- if (get_opt_bool(this_opt, "accel", &accel))
- ;
- else if (get_opt_int(this_opt, "vram", &vram))
- ;
- else if (get_opt_bool(this_opt, "hwcursor", &hwcursor))
- ;
- else if (get_opt_bool(this_opt, "mtrr", &mtrr))
- ;
- else if (get_opt_bool(this_opt, "fixed", &fixed))
- ;
- else if (get_opt_bool(this_opt, "init", &noinit))
- noinit = !noinit;
- else if (OPT_EQUAL(this_opt, "mode="))
- mode = get_opt_string(this_opt, "mode=");
- else
- mode = this_opt;
- }
-
- return 0;
-}
-
-#endif
-
-static int __init intelfb_init(void)
-{
-#ifndef MODULE
- char *option = NULL;
-#endif
-
- DBG_MSG("intelfb_init\n");
-
- INF_MSG("Framebuffer driver for "
- "Intel(R) " SUPPORTED_CHIPSETS " chipsets\n");
- INF_MSG("Version " INTELFB_VERSION "\n");
-
- if (idonly)
- return -ENODEV;
-
- if (fb_modesetting_disabled("intelfb"))
- return -ENODEV;
-
-#ifndef MODULE
- if (fb_get_options("intelfb", &option))
- return -ENODEV;
- intelfb_setup(option);
-#endif
-
- return pci_register_driver(&intelfb_driver);
-}
-
-static void __exit intelfb_exit(void)
-{
- DBG_MSG("intelfb_exit\n");
- pci_unregister_driver(&intelfb_driver);
-}
-
-module_init(intelfb_init);
-module_exit(intelfb_exit);
-
-/***************************************************************
- * driver init / cleanup *
- ***************************************************************/
-
-static void cleanup(struct intelfb_info *dinfo)
-{
- DBG_MSG("cleanup\n");
-
- if (!dinfo)
- return;
-
- intelfbhw_disable_irq(dinfo);
-
- fb_dealloc_cmap(&dinfo->info->cmap);
- kfree(dinfo->info->pixmap.addr);
-
- if (dinfo->registered)
- unregister_framebuffer(dinfo->info);
-
- arch_phys_wc_del(dinfo->wc_cookie);
-
- if (dinfo->fbmem_gart && dinfo->gtt_fb_mem) {
- agp_unbind_memory(dinfo->gtt_fb_mem);
- agp_free_memory(dinfo->gtt_fb_mem);
- }
- if (dinfo->gtt_cursor_mem) {
- agp_unbind_memory(dinfo->gtt_cursor_mem);
- agp_free_memory(dinfo->gtt_cursor_mem);
- }
- if (dinfo->gtt_ring_mem) {
- agp_unbind_memory(dinfo->gtt_ring_mem);
- agp_free_memory(dinfo->gtt_ring_mem);
- }
-
-#ifdef CONFIG_FB_INTEL_I2C
- /* un-register I2C bus */
- intelfb_delete_i2c_busses(dinfo);
-#endif
-
- if (dinfo->mmio_base)
- iounmap((void __iomem *)dinfo->mmio_base);
- if (dinfo->aperture.virtual)
- iounmap((void __iomem *)dinfo->aperture.virtual);
-
- if (dinfo->flag & INTELFB_MMIO_ACQUIRED)
- release_mem_region(dinfo->mmio_base_phys, INTEL_REG_SIZE);
- if (dinfo->flag & INTELFB_FB_ACQUIRED)
- release_mem_region(dinfo->aperture.physical,
- dinfo->aperture.size);
- framebuffer_release(dinfo->info);
-}
-
-#define bailout(dinfo) do { \
- DBG_MSG("bailout\n"); \
- cleanup(dinfo); \
- INF_MSG("Not going to register framebuffer, exiting...\n"); \
- return -ENODEV; \
-} while (0)
-
-
-static int intelfb_pci_register(struct pci_dev *pdev,
- const struct pci_device_id *ent)
-{
- struct fb_info *info;
- struct intelfb_info *dinfo;
- int i, err, dvo;
- int aperture_size, stolen_size = 0;
- struct agp_kern_info gtt_info;
- int agp_memtype;
- const char *s;
- struct agp_bridge_data *bridge;
- int aperture_bar = 0;
- int mmio_bar = 1;
- int offset;
-
- DBG_MSG("intelfb_pci_register\n");
-
- err = aperture_remove_conflicting_pci_devices(pdev, "intelfb");
- if (err)
- return err;
-
- num_registered++;
- if (num_registered != 1) {
- ERR_MSG("Attempted to register %d devices "
- "(should be only 1).\n", num_registered);
- return -ENODEV;
- }
-
- info = framebuffer_alloc(sizeof(struct intelfb_info), &pdev->dev);
- if (!info)
- return -ENOMEM;
-
- if (fb_alloc_cmap(&info->cmap, 256, 1) < 0) {
- ERR_MSG("Could not allocate cmap for intelfb_info.\n");
- goto err_out_cmap;
- }
-
- dinfo = info->par;
- dinfo->info = info;
- dinfo->fbops = &intel_fb_ops;
- dinfo->pdev = pdev;
-
- /* Reserve pixmap space. */
- info->pixmap.addr = kzalloc(64 * 1024, GFP_KERNEL);
- if (info->pixmap.addr == NULL) {
- ERR_MSG("Cannot reserve pixmap memory.\n");
- goto err_out_pixmap;
- }
-
- /* set early this option because it could be changed by tv encoder
- driver */
- dinfo->fixed_mode = fixed;
-
- /* Enable device. */
- if ((err = pci_enable_device(pdev))) {
- ERR_MSG("Cannot enable device.\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- /* Set base addresses. */
- if ((ent->device == PCI_DEVICE_ID_INTEL_915G) ||
- (ent->device == PCI_DEVICE_ID_INTEL_915GM) ||
- (ent->device == PCI_DEVICE_ID_INTEL_945G) ||
- (ent->device == PCI_DEVICE_ID_INTEL_945GM) ||
- (ent->device == PCI_DEVICE_ID_INTEL_945GME) ||
- (ent->device == PCI_DEVICE_ID_INTEL_965G) ||
- (ent->device == PCI_DEVICE_ID_INTEL_965GM)) {
-
- aperture_bar = 2;
- mmio_bar = 0;
- }
- dinfo->aperture.physical = pci_resource_start(pdev, aperture_bar);
- dinfo->aperture.size = pci_resource_len(pdev, aperture_bar);
- dinfo->mmio_base_phys = pci_resource_start(pdev, mmio_bar);
- DBG_MSG("fb aperture: 0x%llx/0x%llx, MMIO region: 0x%llx/0x%llx\n",
- (unsigned long long)pci_resource_start(pdev, aperture_bar),
- (unsigned long long)pci_resource_len(pdev, aperture_bar),
- (unsigned long long)pci_resource_start(pdev, mmio_bar),
- (unsigned long long)pci_resource_len(pdev, mmio_bar));
-
- /* Reserve the fb and MMIO regions */
- if (!request_mem_region(dinfo->aperture.physical, dinfo->aperture.size,
- INTELFB_MODULE_NAME)) {
- ERR_MSG("Cannot reserve FB region.\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- dinfo->flag |= INTELFB_FB_ACQUIRED;
-
- if (!request_mem_region(dinfo->mmio_base_phys,
- INTEL_REG_SIZE,
- INTELFB_MODULE_NAME)) {
- ERR_MSG("Cannot reserve MMIO region.\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- dinfo->flag |= INTELFB_MMIO_ACQUIRED;
-
- /* Get the chipset info. */
- dinfo->pci_chipset = pdev->device;
-
- if (intelfbhw_get_chipset(pdev, dinfo)) {
- cleanup(dinfo);
- return -ENODEV;
- }
-
- if (intelfbhw_get_memory(pdev, &aperture_size, &stolen_size)) {
- cleanup(dinfo);
- return -ENODEV;
- }
-
- INF_MSG("%02x:%02x.%d: %s, aperture size %dMB, "
- "stolen memory %dkB\n",
- pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn), dinfo->name,
- BtoMB(aperture_size), BtoKB(stolen_size));
-
- /* Set these from the options. */
- dinfo->accel = accel;
- dinfo->hwcursor = hwcursor;
-
- if (NOACCEL_CHIPSET(dinfo) && dinfo->accel == 1) {
- INF_MSG("Acceleration is not supported for the %s chipset.\n",
- dinfo->name);
- dinfo->accel = 0;
- }
-
- /* Framebuffer parameters - Use all the stolen memory if >= vram */
- if (ROUND_UP_TO_PAGE(stolen_size) >= MB(vram)) {
- dinfo->fb.size = ROUND_UP_TO_PAGE(stolen_size);
- dinfo->fbmem_gart = 0;
- } else {
- dinfo->fb.size = MB(vram);
- dinfo->fbmem_gart = 1;
- }
-
- /* Allocate space for the ring buffer and HW cursor if enabled. */
- if (dinfo->accel) {
- dinfo->ring.size = RINGBUFFER_SIZE;
- dinfo->ring_tail_mask = dinfo->ring.size - 1;
- }
- if (dinfo->hwcursor)
- dinfo->cursor.size = HW_CURSOR_SIZE;
-
- /* Use agpgart to manage the GATT */
- if (!(bridge = agp_backend_acquire(pdev))) {
- ERR_MSG("cannot acquire agp\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- /* get the current gatt info */
- if (agp_copy_info(bridge, &gtt_info)) {
- ERR_MSG("cannot get agp info\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -ENODEV;
- }
-
- if (MB(voffset) < stolen_size)
- offset = (stolen_size >> 12);
- else
- offset = ROUND_UP_TO_PAGE(MB(voffset))/GTT_PAGE_SIZE;
-
- /* set the mem offsets - set them after the already used pages */
- if (dinfo->accel)
- dinfo->ring.offset = offset + gtt_info.current_memory;
- if (dinfo->hwcursor)
- dinfo->cursor.offset = offset +
- + gtt_info.current_memory + (dinfo->ring.size >> 12);
- if (dinfo->fbmem_gart)
- dinfo->fb.offset = offset +
- + gtt_info.current_memory + (dinfo->ring.size >> 12)
- + (dinfo->cursor.size >> 12);
-
- /* Allocate memories (which aren't stolen) */
- /* Map the fb and MMIO regions */
- /* ioremap only up to the end of used aperture */
- dinfo->aperture.virtual = (u8 __iomem *)ioremap_wc
- (dinfo->aperture.physical, ((offset + dinfo->fb.offset) << 12)
- + dinfo->fb.size);
- if (!dinfo->aperture.virtual) {
- ERR_MSG("Cannot remap FB region.\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -ENODEV;
- }
-
- dinfo->mmio_base =
- (u8 __iomem *)ioremap(dinfo->mmio_base_phys,
- INTEL_REG_SIZE);
- if (!dinfo->mmio_base) {
- ERR_MSG("Cannot remap MMIO region.\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -ENODEV;
- }
-
- if (dinfo->accel) {
- if (!(dinfo->gtt_ring_mem =
- agp_allocate_memory(bridge, dinfo->ring.size >> 12,
- AGP_NORMAL_MEMORY))) {
- ERR_MSG("cannot allocate ring buffer memory\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -ENOMEM;
- }
- if (agp_bind_memory(dinfo->gtt_ring_mem,
- dinfo->ring.offset)) {
- ERR_MSG("cannot bind ring buffer memory\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -EBUSY;
- }
- dinfo->ring.physical = dinfo->aperture.physical
- + (dinfo->ring.offset << 12);
- dinfo->ring.virtual = dinfo->aperture.virtual
- + (dinfo->ring.offset << 12);
- dinfo->ring_head = 0;
- }
- if (dinfo->hwcursor) {
- agp_memtype = dinfo->mobile ? AGP_PHYSICAL_MEMORY
- : AGP_NORMAL_MEMORY;
- if (!(dinfo->gtt_cursor_mem =
- agp_allocate_memory(bridge, dinfo->cursor.size >> 12,
- agp_memtype))) {
- ERR_MSG("cannot allocate cursor memory\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -ENOMEM;
- }
- if (agp_bind_memory(dinfo->gtt_cursor_mem,
- dinfo->cursor.offset)) {
- ERR_MSG("cannot bind cursor memory\n");
- agp_backend_release(bridge);
- cleanup(dinfo);
- return -EBUSY;
- }
- if (dinfo->mobile)
- dinfo->cursor.physical
- = dinfo->gtt_cursor_mem->physical;
- else
- dinfo->cursor.physical = dinfo->aperture.physical
- + (dinfo->cursor.offset << 12);
- dinfo->cursor.virtual = dinfo->aperture.virtual
- + (dinfo->cursor.offset << 12);
- }
- if (dinfo->fbmem_gart) {
- if (!(dinfo->gtt_fb_mem =
- agp_allocate_memory(bridge, dinfo->fb.size >> 12,
- AGP_NORMAL_MEMORY))) {
- WRN_MSG("cannot allocate framebuffer memory - use "
- "the stolen one\n");
- dinfo->fbmem_gart = 0;
- }
- if (agp_bind_memory(dinfo->gtt_fb_mem,
- dinfo->fb.offset)) {
- WRN_MSG("cannot bind framebuffer memory - use "
- "the stolen one\n");
- dinfo->fbmem_gart = 0;
- }
- }
-
- /* update framebuffer memory parameters */
- if (!dinfo->fbmem_gart)
- dinfo->fb.offset = 0; /* starts at offset 0 */
- dinfo->fb.physical = dinfo->aperture.physical
- + (dinfo->fb.offset << 12);
- dinfo->fb.virtual = dinfo->aperture.virtual + (dinfo->fb.offset << 12);
- dinfo->fb_start = dinfo->fb.offset << 12;
-
- /* release agpgart */
- agp_backend_release(bridge);
-
- if (mtrr)
- dinfo->wc_cookie = arch_phys_wc_add(dinfo->aperture.physical,
- dinfo->aperture.size);
-
- DBG_MSG("fb: 0x%x(+ 0x%x)/0x%x (0x%p)\n",
- dinfo->fb.physical, dinfo->fb.offset, dinfo->fb.size,
- dinfo->fb.virtual);
- DBG_MSG("MMIO: 0x%x/0x%x (0x%p)\n",
- dinfo->mmio_base_phys, INTEL_REG_SIZE,
- dinfo->mmio_base);
- DBG_MSG("ring buffer: 0x%x/0x%x (0x%p)\n",
- dinfo->ring.physical, dinfo->ring.size,
- dinfo->ring.virtual);
- DBG_MSG("HW cursor: 0x%x/0x%x (0x%p) (offset 0x%x) (phys 0x%x)\n",
- dinfo->cursor.physical, dinfo->cursor.size,
- dinfo->cursor.virtual, dinfo->cursor.offset,
- dinfo->cursor.physical);
-
- DBG_MSG("options: vram = %d, accel = %d, hwcursor = %d, fixed = %d, "
- "noinit = %d\n", vram, accel, hwcursor, fixed, noinit);
- DBG_MSG("options: mode = \"%s\"\n", mode ? mode : "");
-
- if (probeonly)
- bailout(dinfo);
-
- /*
- * Check if the LVDS port or any DVO ports are enabled. If so,
- * don't allow mode switching
- */
- dvo = intelfbhw_check_non_crt(dinfo);
- if (dvo) {
- dinfo->fixed_mode = 1;
- WRN_MSG("Non-CRT device is enabled ( ");
- i = 0;
- while (dvo) {
- if (dvo & 1) {
- s = intelfbhw_dvo_to_string(1 << i);
- if (s)
- printk("%s ", s);
- }
- dvo >>= 1;
- ++i;
- }
- printk("). Disabling mode switching.\n");
- }
-
- if (bailearly == 1)
- bailout(dinfo);
-
- if (FIXED_MODE(dinfo) &&
- screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB) {
- ERR_MSG("Video mode must be programmed at boot time.\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- if (bailearly == 2)
- bailout(dinfo);
-
- /* Initialise dinfo and related data. */
- /* If an initial mode was programmed at boot time, get its details. */
- if (screen_info.orig_video_isVGA == VIDEO_TYPE_VLFB)
- get_initial_mode(dinfo);
-
- if (bailearly == 3)
- bailout(dinfo);
-
- if (FIXED_MODE(dinfo)) /* remap fb address */
- update_dinfo(dinfo, &dinfo->initial_var);
-
- if (bailearly == 4)
- bailout(dinfo);
-
-
- if (intelfb_set_fbinfo(dinfo)) {
- cleanup(dinfo);
- return -ENODEV;
- }
-
- if (bailearly == 5)
- bailout(dinfo);
-
-#ifdef CONFIG_FB_INTEL_I2C
- /* register I2C bus */
- intelfb_create_i2c_busses(dinfo);
-#endif
-
- if (bailearly == 6)
- bailout(dinfo);
-
- pci_set_drvdata(pdev, dinfo);
-
- /* Save the initial register state. */
- i = intelfbhw_read_hw_state(dinfo, &dinfo->save_state,
- bailearly > 6 ? bailearly - 6 : 0);
- if (i != 0) {
- DBG_MSG("intelfbhw_read_hw_state returned %d\n", i);
- bailout(dinfo);
- }
-
- intelfbhw_print_hw_state(dinfo, &dinfo->save_state);
-
- if (bailearly == 18)
- bailout(dinfo);
-
- /* read active pipe */
- dinfo->pipe = intelfbhw_active_pipe(&dinfo->save_state);
-
- /* Cursor initialisation */
- if (dinfo->hwcursor) {
- intelfbhw_cursor_init(dinfo);
- intelfbhw_cursor_reset(dinfo);
- }
-
- if (bailearly == 19)
- bailout(dinfo);
-
- /* 2d acceleration init */
- if (dinfo->accel)
- intelfbhw_2d_start(dinfo);
-
- if (bailearly == 20)
- bailout(dinfo);
-
- if (noregister)
- bailout(dinfo);
-
- if (register_framebuffer(dinfo->info) < 0) {
- ERR_MSG("Cannot register framebuffer.\n");
- cleanup(dinfo);
- return -ENODEV;
- }
-
- dinfo->registered = 1;
- dinfo->open = 0;
-
- init_waitqueue_head(&dinfo->vsync.wait);
- spin_lock_init(&dinfo->int_lock);
- dinfo->irq_flags = 0;
- dinfo->vsync.pan_display = 0;
- dinfo->vsync.pan_offset = 0;
-
- return 0;
-
-err_out_pixmap:
- fb_dealloc_cmap(&info->cmap);
-err_out_cmap:
- framebuffer_release(info);
- return -ENODEV;
-}
-
-static void intelfb_pci_unregister(struct pci_dev *pdev)
-{
- struct intelfb_info *dinfo = pci_get_drvdata(pdev);
-
- DBG_MSG("intelfb_pci_unregister\n");
-
- if (!dinfo)
- return;
-
- cleanup(dinfo);
-}
-
-/***************************************************************
- * helper functions *
- ***************************************************************/
-
-__inline__ int intelfb_var_to_depth(const struct fb_var_screeninfo *var)
-{
- DBG_MSG("intelfb_var_to_depth: bpp: %d, green.length is %d\n",
- var->bits_per_pixel, var->green.length);
-
- switch (var->bits_per_pixel) {
- case 16:
- return (var->green.length == 6) ? 16 : 15;
- case 32:
- return 24;
- default:
- return var->bits_per_pixel;
- }
-}
-
-
-static __inline__ int var_to_refresh(const struct fb_var_screeninfo *var)
-{
- int xtot = var->xres + var->left_margin + var->right_margin +
- var->hsync_len;
- int ytot = var->yres + var->upper_margin + var->lower_margin +
- var->vsync_len;
-
- return (1000000000 / var->pixclock * 1000 + 500) / xtot / ytot;
-}
-
-/***************************************************************
- * Various initialisation functions *
- ***************************************************************/
-
-static void get_initial_mode(struct intelfb_info *dinfo)
-{
- struct fb_var_screeninfo *var;
- int xtot, ytot;
-
- DBG_MSG("get_initial_mode\n");
-
- dinfo->initial_vga = 1;
- dinfo->initial_fb_base = screen_info.lfb_base;
- dinfo->initial_video_ram = screen_info.lfb_size * KB(64);
- dinfo->initial_pitch = screen_info.lfb_linelength;
-
- var = &dinfo->initial_var;
- memset(var, 0, sizeof(*var));
- var->xres = screen_info.lfb_width;
- var->yres = screen_info.lfb_height;
- var->bits_per_pixel = screen_info.lfb_depth;
- switch (screen_info.lfb_depth) {
- case 15:
- var->bits_per_pixel = 16;
- break;
- case 24:
- var->bits_per_pixel = 32;
- break;
- }
-
- DBG_MSG("Initial info: FB is 0x%x/0x%x (%d kByte)\n",
- dinfo->initial_fb_base, dinfo->initial_video_ram,
- BtoKB(dinfo->initial_video_ram));
-
- DBG_MSG("Initial info: mode is %dx%d-%d (%d)\n",
- var->xres, var->yres, var->bits_per_pixel,
- dinfo->initial_pitch);
-
- /* Dummy timing values (assume 60Hz) */
- var->left_margin = (var->xres / 8) & 0xf8;
- var->right_margin = 32;
- var->upper_margin = 16;
- var->lower_margin = 4;
- var->hsync_len = (var->xres / 8) & 0xf8;
- var->vsync_len = 4;
-
- xtot = var->xres + var->left_margin +
- var->right_margin + var->hsync_len;
- ytot = var->yres + var->upper_margin +
- var->lower_margin + var->vsync_len;
- var->pixclock = 10000000 / xtot * 1000 / ytot * 100 / 60;
-
- var->height = -1;
- var->width = -1;
-
- if (var->bits_per_pixel > 8) {
- var->red.offset = screen_info.red_pos;
- var->red.length = screen_info.red_size;
- var->green.offset = screen_info.green_pos;
- var->green.length = screen_info.green_size;
- var->blue.offset = screen_info.blue_pos;
- var->blue.length = screen_info.blue_size;
- var->transp.offset = screen_info.rsvd_pos;
- var->transp.length = screen_info.rsvd_size;
- } else {
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- }
-}
-
-static int intelfb_init_var(struct intelfb_info *dinfo)
-{
- struct fb_var_screeninfo *var;
- int msrc = 0;
-
- DBG_MSG("intelfb_init_var\n");
-
- var = &dinfo->info->var;
- if (FIXED_MODE(dinfo)) {
- memcpy(var, &dinfo->initial_var,
- sizeof(struct fb_var_screeninfo));
- msrc = 5;
- } else {
- const u8 *edid_s = fb_firmware_edid(&dinfo->pdev->dev);
- u8 *edid_d = NULL;
-
- if (edid_s) {
- edid_d = kmemdup(edid_s, EDID_LENGTH, GFP_KERNEL);
-
- if (edid_d) {
- fb_edid_to_monspecs(edid_d,
- &dinfo->info->monspecs);
- kfree(edid_d);
- }
- }
-
- if (mode) {
- printk("intelfb: Looking for mode in private "
- "database\n");
- msrc = fb_find_mode(var, dinfo->info, mode,
- dinfo->info->monspecs.modedb,
- dinfo->info->monspecs.modedb_len,
- NULL, 0);
-
- if (msrc && msrc > 1) {
- printk("intelfb: No mode in private database, "
- "intelfb: looking for mode in global "
- "database ");
- msrc = fb_find_mode(var, dinfo->info, mode,
- NULL, 0, NULL, 0);
-
- if (msrc)
- msrc |= 8;
- }
-
- }
-
- if (!msrc)
- msrc = fb_find_mode(var, dinfo->info, PREFERRED_MODE,
- NULL, 0, NULL, 0);
- }
-
- if (!msrc) {
- ERR_MSG("Cannot find a suitable video mode.\n");
- return 1;
- }
-
- INF_MSG("Initial video mode is %dx%d-%d@%d.\n", var->xres, var->yres,
- var->bits_per_pixel, var_to_refresh(var));
-
- DBG_MSG("Initial video mode is from %d.\n", msrc);
-
-#if ALLOCATE_FOR_PANNING
- /* Allow use of half of the video ram for panning */
- var->xres_virtual = var->xres;
- var->yres_virtual =
- dinfo->fb.size / 2 / (var->bits_per_pixel * var->xres);
- if (var->yres_virtual < var->yres)
- var->yres_virtual = var->yres;
-#else
- var->yres_virtual = var->yres;
-#endif
-
- if (dinfo->accel)
- var->accel_flags |= FB_ACCELF_TEXT;
- else
- var->accel_flags &= ~FB_ACCELF_TEXT;
-
- return 0;
-}
-
-static int intelfb_set_fbinfo(struct intelfb_info *dinfo)
-{
- struct fb_info *info = dinfo->info;
-
- DBG_MSG("intelfb_set_fbinfo\n");
-
- info->fbops = &intel_fb_ops;
- info->pseudo_palette = dinfo->pseudo_palette;
-
- info->pixmap.size = 64*1024;
- info->pixmap.buf_align = 8;
- info->pixmap.access_align = 32;
- info->pixmap.flags = FB_PIXMAP_SYSTEM;
-
- if (intelfb_init_var(dinfo))
- return 1;
-
- info->pixmap.scan_align = 1;
- strcpy(info->fix.id, dinfo->name);
- info->fix.smem_start = dinfo->fb.physical;
- info->fix.smem_len = dinfo->fb.size;
- info->fix.type = FB_TYPE_PACKED_PIXELS;
- info->fix.type_aux = 0;
- info->fix.xpanstep = 8;
- info->fix.ypanstep = 1;
- info->fix.ywrapstep = 0;
- info->fix.mmio_start = dinfo->mmio_base_phys;
- info->fix.mmio_len = INTEL_REG_SIZE;
- info->fix.accel = FB_ACCEL_I830;
- update_dinfo(dinfo, &info->var);
-
- return 0;
-}
-
-/* Update dinfo to match the active video mode. */
-static void update_dinfo(struct intelfb_info *dinfo,
- struct fb_var_screeninfo *var)
-{
- DBG_MSG("update_dinfo\n");
-
- dinfo->bpp = var->bits_per_pixel;
- dinfo->depth = intelfb_var_to_depth(var);
- dinfo->xres = var->xres;
- dinfo->yres = var->xres;
- dinfo->pixclock = var->pixclock;
-
- dinfo->info->fix.visual = dinfo->visual;
- dinfo->info->fix.line_length = dinfo->pitch;
-
- switch (dinfo->bpp) {
- case 8:
- dinfo->visual = FB_VISUAL_PSEUDOCOLOR;
- dinfo->pitch = var->xres_virtual;
- break;
- case 16:
- dinfo->visual = FB_VISUAL_TRUECOLOR;
- dinfo->pitch = var->xres_virtual * 2;
- break;
- case 32:
- dinfo->visual = FB_VISUAL_TRUECOLOR;
- dinfo->pitch = var->xres_virtual * 4;
- break;
- }
-
- /* Make sure the line length is a aligned correctly. */
- if (IS_I9XX(dinfo))
- dinfo->pitch = ROUND_UP_TO(dinfo->pitch, STRIDE_ALIGNMENT_I9XX);
- else
- dinfo->pitch = ROUND_UP_TO(dinfo->pitch, STRIDE_ALIGNMENT);
-
- if (FIXED_MODE(dinfo))
- dinfo->pitch = dinfo->initial_pitch;
-
- dinfo->info->screen_base = (char __iomem *)dinfo->fb.virtual;
- dinfo->info->fix.line_length = dinfo->pitch;
- dinfo->info->fix.visual = dinfo->visual;
-}
-
-/* fbops functions */
-
-/***************************************************************
- * fbdev interface *
- ***************************************************************/
-
-static int intelfb_open(struct fb_info *info, int user)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
-
- if (user)
- dinfo->open++;
-
- return 0;
-}
-
-static int intelfb_release(struct fb_info *info, int user)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
-
- if (user) {
- dinfo->open--;
- msleep(1);
- if (!dinfo->open)
- intelfbhw_disable_irq(dinfo);
- }
-
- return 0;
-}
-
-static int intelfb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- int change_var = 0;
- struct fb_var_screeninfo v;
- struct intelfb_info *dinfo;
- static int first = 1;
- int i;
- /* Good pitches to allow tiling. Don't care about pitches < 1024. */
- static const int pitches[] = {
- 128 * 8,
- 128 * 16,
- 128 * 32,
- 128 * 64,
- 0
- };
-
- DBG_MSG("intelfb_check_var: accel_flags is %d\n", var->accel_flags);
-
- dinfo = GET_DINFO(info);
-
- if (!var->pixclock)
- return -EINVAL;
-
- /* update the pitch */
- if (intelfbhw_validate_mode(dinfo, var) != 0)
- return -EINVAL;
-
- v = *var;
-
- for (i = 0; pitches[i] != 0; i++) {
- if (pitches[i] >= v.xres_virtual) {
- v.xres_virtual = pitches[i];
- break;
- }
- }
-
- /* Check for a supported bpp. */
- if (v.bits_per_pixel <= 8)
- v.bits_per_pixel = 8;
- else if (v.bits_per_pixel <= 16) {
- if (v.bits_per_pixel == 16)
- v.green.length = 6;
- v.bits_per_pixel = 16;
- } else if (v.bits_per_pixel <= 32)
- v.bits_per_pixel = 32;
- else
- return -EINVAL;
-
- change_var = ((info->var.xres != var->xres) ||
- (info->var.yres != var->yres) ||
- (info->var.xres_virtual != var->xres_virtual) ||
- (info->var.yres_virtual != var->yres_virtual) ||
- (info->var.bits_per_pixel != var->bits_per_pixel) ||
- memcmp(&info->var.red, &var->red, sizeof(var->red)) ||
- memcmp(&info->var.green, &var->green,
- sizeof(var->green)) ||
- memcmp(&info->var.blue, &var->blue, sizeof(var->blue)));
-
- if (FIXED_MODE(dinfo) &&
- (change_var ||
- var->yres_virtual > dinfo->initial_var.yres_virtual ||
- var->yres_virtual < dinfo->initial_var.yres ||
- var->xoffset || var->nonstd)) {
- if (first) {
- ERR_MSG("Changing the video mode is not supported.\n");
- first = 0;
- }
- return -EINVAL;
- }
-
- switch (intelfb_var_to_depth(&v)) {
- case 8:
- v.red.offset = v.green.offset = v.blue.offset = 0;
- v.red.length = v.green.length = v.blue.length = 8;
- v.transp.offset = v.transp.length = 0;
- break;
- case 15:
- v.red.offset = 10;
- v.green.offset = 5;
- v.blue.offset = 0;
- v.red.length = v.green.length = v.blue.length = 5;
- v.transp.offset = v.transp.length = 0;
- break;
- case 16:
- v.red.offset = 11;
- v.green.offset = 5;
- v.blue.offset = 0;
- v.red.length = 5;
- v.green.length = 6;
- v.blue.length = 5;
- v.transp.offset = v.transp.length = 0;
- break;
- case 24:
- v.red.offset = 16;
- v.green.offset = 8;
- v.blue.offset = 0;
- v.red.length = v.green.length = v.blue.length = 8;
- v.transp.offset = v.transp.length = 0;
- break;
- case 32:
- v.red.offset = 16;
- v.green.offset = 8;
- v.blue.offset = 0;
- v.red.length = v.green.length = v.blue.length = 8;
- v.transp.offset = 24;
- v.transp.length = 8;
- break;
- }
-
- if (v.xoffset > v.xres_virtual - v.xres)
- v.xoffset = v.xres_virtual - v.xres;
- if (v.yoffset > v.yres_virtual - v.yres)
- v.yoffset = v.yres_virtual - v.yres;
-
- v.red.msb_right = v.green.msb_right = v.blue.msb_right =
- v.transp.msb_right = 0;
-
- *var = v;
-
- return 0;
-}
-
-static int intelfb_set_par(struct fb_info *info)
-{
- struct intelfb_hwstate *hw;
- struct intelfb_info *dinfo = GET_DINFO(info);
-
- if (FIXED_MODE(dinfo)) {
- ERR_MSG("Changing the video mode is not supported.\n");
- return -EINVAL;
- }
-
- hw = kmalloc(sizeof(*hw), GFP_ATOMIC);
- if (!hw)
- return -ENOMEM;
-
- DBG_MSG("intelfb_set_par (%dx%d-%d)\n", info->var.xres,
- info->var.yres, info->var.bits_per_pixel);
-
- /*
- * Disable VCO prior to timing register change.
- */
- OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE);
-
- intelfb_blank(FB_BLANK_POWERDOWN, info);
-
- if (ACCEL(dinfo, info))
- intelfbhw_2d_stop(dinfo);
-
- memcpy(hw, &dinfo->save_state, sizeof(*hw));
- if (intelfbhw_mode_to_hw(dinfo, hw, &info->var))
- goto invalid_mode;
- if (intelfbhw_program_mode(dinfo, hw, 0))
- goto invalid_mode;
-
-#if REGDUMP > 0
- intelfbhw_read_hw_state(dinfo, hw, 0);
- intelfbhw_print_hw_state(dinfo, hw);
-#endif
-
- update_dinfo(dinfo, &info->var);
-
- if (ACCEL(dinfo, info))
- intelfbhw_2d_start(dinfo);
-
- intelfb_pan_display(&info->var, info);
-
- intelfb_blank(FB_BLANK_UNBLANK, info);
-
- if (ACCEL(dinfo, info)) {
- info->flags = FBINFO_HWACCEL_YPAN |
- FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
- FBINFO_HWACCEL_IMAGEBLIT;
- } else
- info->flags = FBINFO_HWACCEL_YPAN;
-
- kfree(hw);
- return 0;
-invalid_mode:
- kfree(hw);
- return -EINVAL;
-}
-
-static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
-
-#if VERBOSE > 0
- DBG_MSG("intelfb_setcolreg: regno %d, depth %d\n", regno, dinfo->depth);
-#endif
-
- if (regno > 255)
- return 1;
-
- if (dinfo->depth == 8) {
- red >>= 8;
- green >>= 8;
- blue >>= 8;
-
- intelfbhw_setcolreg(dinfo, regno, red, green, blue,
- transp);
- }
-
- if (regno < 16) {
- switch (dinfo->depth) {
- case 15:
- dinfo->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
- ((green & 0xf800) >> 6) |
- ((blue & 0xf800) >> 11);
- break;
- case 16:
- dinfo->pseudo_palette[regno] = (red & 0xf800) |
- ((green & 0xfc00) >> 5) |
- ((blue & 0xf800) >> 11);
- break;
- case 24:
- dinfo->pseudo_palette[regno] = ((red & 0xff00) << 8) |
- (green & 0xff00) |
- ((blue & 0xff00) >> 8);
- break;
- }
- }
-
- return 0;
-}
-
-static int intelfb_blank(int blank, struct fb_info *info)
-{
- intelfbhw_do_blank(blank, info);
- return 0;
-}
-
-static int intelfb_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- intelfbhw_pan_display(var, info);
- return 0;
-}
-
-/* When/if we have our own ioctls. */
-static int intelfb_ioctl(struct fb_info *info, unsigned int cmd,
- unsigned long arg)
-{
- int retval = 0;
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 pipe = 0;
-
- switch (cmd) {
- case FBIO_WAITFORVSYNC:
- if (get_user(pipe, (__u32 __user *)arg))
- return -EFAULT;
-
- retval = intelfbhw_wait_for_vsync(dinfo, pipe);
- break;
- default:
- break;
- }
-
- return retval;
-}
-
-static void intelfb_fillrect (struct fb_info *info,
- const struct fb_fillrect *rect)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 rop, color;
-
-#if VERBOSE > 0
- DBG_MSG("intelfb_fillrect\n");
-#endif
-
- if (!ACCEL(dinfo, info) || dinfo->depth == 4) {
- cfb_fillrect(info, rect);
- return;
- }
-
- if (rect->rop == ROP_COPY)
- rop = PAT_ROP_GXCOPY;
- else /* ROP_XOR */
- rop = PAT_ROP_GXXOR;
-
- if (dinfo->depth != 8)
- color = dinfo->pseudo_palette[rect->color];
- else
- color = rect->color;
-
- intelfbhw_do_fillrect(dinfo, rect->dx, rect->dy,
- rect->width, rect->height, color,
- dinfo->pitch, info->var.bits_per_pixel,
- rop);
-}
-
-static void intelfb_copyarea(struct fb_info *info,
- const struct fb_copyarea *region)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
-
-#if VERBOSE > 0
- DBG_MSG("intelfb_copyarea\n");
-#endif
-
- if (!ACCEL(dinfo, info) || dinfo->depth == 4) {
- cfb_copyarea(info, region);
- return;
- }
-
- intelfbhw_do_bitblt(dinfo, region->sx, region->sy, region->dx,
- region->dy, region->width, region->height,
- dinfo->pitch, info->var.bits_per_pixel);
-}
-
-static void intelfb_imageblit(struct fb_info *info,
- const struct fb_image *image)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 fgcolor, bgcolor;
-
-#if VERBOSE > 0
- DBG_MSG("intelfb_imageblit\n");
-#endif
-
- if (!ACCEL(dinfo, info) || dinfo->depth == 4
- || image->depth != 1) {
- cfb_imageblit(info, image);
- return;
- }
-
- if (dinfo->depth != 8) {
- fgcolor = dinfo->pseudo_palette[image->fg_color];
- bgcolor = dinfo->pseudo_palette[image->bg_color];
- } else {
- fgcolor = image->fg_color;
- bgcolor = image->bg_color;
- }
-
- if (!intelfbhw_do_drawglyph(dinfo, fgcolor, bgcolor, image->width,
- image->height, image->data,
- image->dx, image->dy,
- dinfo->pitch, info->var.bits_per_pixel)) {
- cfb_imageblit(info, image);
- return;
- }
-}
-
-static int intelfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 physical;
-#if VERBOSE > 0
- DBG_MSG("intelfb_cursor\n");
-#endif
-
- if (!dinfo->hwcursor)
- return -ENODEV;
-
- intelfbhw_cursor_hide(dinfo);
-
- /* If XFree killed the cursor - restore it */
- physical = (dinfo->mobile || IS_I9XX(dinfo)) ? dinfo->cursor.physical :
- (dinfo->cursor.offset << 12);
-
- if (INREG(CURSOR_A_BASEADDR) != physical) {
- u32 fg, bg;
-
- DBG_MSG("the cursor was killed - restore it !!\n");
- DBG_MSG("size %d, %d pos %d, %d\n",
- cursor->image.width, cursor->image.height,
- cursor->image.dx, cursor->image.dy);
-
- intelfbhw_cursor_init(dinfo);
- intelfbhw_cursor_reset(dinfo);
- intelfbhw_cursor_setpos(dinfo, cursor->image.dx,
- cursor->image.dy);
-
- if (dinfo->depth != 8) {
- fg =dinfo->pseudo_palette[cursor->image.fg_color];
- bg =dinfo->pseudo_palette[cursor->image.bg_color];
- } else {
- fg = cursor->image.fg_color;
- bg = cursor->image.bg_color;
- }
- intelfbhw_cursor_setcolor(dinfo, bg, fg);
- intelfbhw_cursor_load(dinfo, cursor->image.width,
- cursor->image.height,
- dinfo->cursor_src);
-
- if (cursor->enable)
- intelfbhw_cursor_show(dinfo);
- return 0;
- }
-
- if (cursor->set & FB_CUR_SETPOS) {
- u32 dx, dy;
-
- dx = cursor->image.dx - info->var.xoffset;
- dy = cursor->image.dy - info->var.yoffset;
-
- intelfbhw_cursor_setpos(dinfo, dx, dy);
- }
-
- if (cursor->set & FB_CUR_SETSIZE) {
- if (cursor->image.width > 64 || cursor->image.height > 64)
- return -ENXIO;
-
- intelfbhw_cursor_reset(dinfo);
- }
-
- if (cursor->set & FB_CUR_SETCMAP) {
- u32 fg, bg;
-
- if (dinfo->depth != 8) {
- fg = dinfo->pseudo_palette[cursor->image.fg_color];
- bg = dinfo->pseudo_palette[cursor->image.bg_color];
- } else {
- fg = cursor->image.fg_color;
- bg = cursor->image.bg_color;
- }
-
- intelfbhw_cursor_setcolor(dinfo, bg, fg);
- }
-
- if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
- u32 s_pitch = (ROUND_UP_TO(cursor->image.width, 8) / 8);
- u32 size = s_pitch * cursor->image.height;
- u8 *dat = (u8 *) cursor->image.data;
- u8 *msk = (u8 *) cursor->mask;
- u8 src[64];
- u32 i;
-
- if (cursor->image.depth != 1)
- return -ENXIO;
-
- switch (cursor->rop) {
- case ROP_XOR:
- for (i = 0; i < size; i++)
- src[i] = dat[i] ^ msk[i];
- break;
- case ROP_COPY:
- default:
- for (i = 0; i < size; i++)
- src[i] = dat[i] & msk[i];
- break;
- }
-
- /* save the bitmap to restore it when XFree will
- make the cursor dirty */
- memcpy(dinfo->cursor_src, src, size);
-
- intelfbhw_cursor_load(dinfo, cursor->image.width,
- cursor->image.height, src);
- }
-
- if (cursor->enable)
- intelfbhw_cursor_show(dinfo);
-
- return 0;
-}
-
-static int intelfb_sync(struct fb_info *info)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
-
-#if VERBOSE > 0
- DBG_MSG("intelfb_sync\n");
-#endif
-
- if (dinfo->ring_lockup)
- return 0;
-
- intelfbhw_do_sync(dinfo);
- return 0;
-}
-
diff --git a/drivers/video/fbdev/intelfb/intelfbhw.c b/drivers/video/fbdev/intelfb/intelfbhw.c
deleted file mode 100644
index 2086e06532ee..000000000000
--- a/drivers/video/fbdev/intelfb/intelfbhw.c
+++ /dev/null
@@ -1,2115 +0,0 @@
-/*
- * intelfb
- *
- * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
- *
- * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
- * 2004 Sylvain Meyer
- *
- * This driver consists of two parts. The first part (intelfbdrv.c) provides
- * the basic fbdev interfaces, is derived in part from the radeonfb and
- * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
- * provides the code to program the hardware. Most of it is derived from
- * the i810/i830 XFree86 driver. The HW-specific code is covered here
- * under a dual license (GPL and MIT/XFree86 license).
- *
- * Author: David Dawes
- *
- */
-
-/* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/vmalloc.h>
-#include <linux/pagemap.h>
-#include <linux/interrupt.h>
-
-#include <asm/io.h>
-
-#include "intelfb.h"
-#include "intelfbhw.h"
-
-struct pll_min_max {
- int min_m, max_m, min_m1, max_m1;
- int min_m2, max_m2, min_n, max_n;
- int min_p, max_p, min_p1, max_p1;
- int min_vco, max_vco, p_transition_clk, ref_clk;
- int p_inc_lo, p_inc_hi;
-};
-
-#define PLLS_I8xx 0
-#define PLLS_I9xx 1
-#define PLLS_MAX 2
-
-static struct pll_min_max plls[PLLS_MAX] = {
- { 108, 140, 18, 26,
- 6, 16, 3, 16,
- 4, 128, 0, 31,
- 930000, 1400000, 165000, 48000,
- 4, 2 }, /* I8xx */
-
- { 75, 120, 10, 20,
- 5, 9, 4, 7,
- 5, 80, 1, 8,
- 1400000, 2800000, 200000, 96000,
- 10, 5 } /* I9xx */
-};
-
-int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
-{
- u32 tmp;
- if (!pdev || !dinfo)
- return 1;
-
- switch (pdev->device) {
- case PCI_DEVICE_ID_INTEL_830M:
- dinfo->name = "Intel(R) 830M";
- dinfo->chipset = INTEL_830M;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I8xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_845G:
- dinfo->name = "Intel(R) 845G";
- dinfo->chipset = INTEL_845G;
- dinfo->mobile = 0;
- dinfo->pll_index = PLLS_I8xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_854:
- dinfo->mobile = 1;
- dinfo->name = "Intel(R) 854";
- dinfo->chipset = INTEL_854;
- return 0;
- case PCI_DEVICE_ID_INTEL_85XGM:
- tmp = 0;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I8xx;
- pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
- switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
- INTEL_85X_VARIANT_MASK) {
- case INTEL_VAR_855GME:
- dinfo->name = "Intel(R) 855GME";
- dinfo->chipset = INTEL_855GME;
- return 0;
- case INTEL_VAR_855GM:
- dinfo->name = "Intel(R) 855GM";
- dinfo->chipset = INTEL_855GM;
- return 0;
- case INTEL_VAR_852GME:
- dinfo->name = "Intel(R) 852GME";
- dinfo->chipset = INTEL_852GME;
- return 0;
- case INTEL_VAR_852GM:
- dinfo->name = "Intel(R) 852GM";
- dinfo->chipset = INTEL_852GM;
- return 0;
- default:
- dinfo->name = "Intel(R) 852GM/855GM";
- dinfo->chipset = INTEL_85XGM;
- return 0;
- }
- break;
- case PCI_DEVICE_ID_INTEL_865G:
- dinfo->name = "Intel(R) 865G";
- dinfo->chipset = INTEL_865G;
- dinfo->mobile = 0;
- dinfo->pll_index = PLLS_I8xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_915G:
- dinfo->name = "Intel(R) 915G";
- dinfo->chipset = INTEL_915G;
- dinfo->mobile = 0;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_915GM:
- dinfo->name = "Intel(R) 915GM";
- dinfo->chipset = INTEL_915GM;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_945G:
- dinfo->name = "Intel(R) 945G";
- dinfo->chipset = INTEL_945G;
- dinfo->mobile = 0;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_945GM:
- dinfo->name = "Intel(R) 945GM";
- dinfo->chipset = INTEL_945GM;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_945GME:
- dinfo->name = "Intel(R) 945GME";
- dinfo->chipset = INTEL_945GME;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_965G:
- dinfo->name = "Intel(R) 965G";
- dinfo->chipset = INTEL_965G;
- dinfo->mobile = 0;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- case PCI_DEVICE_ID_INTEL_965GM:
- dinfo->name = "Intel(R) 965GM";
- dinfo->chipset = INTEL_965GM;
- dinfo->mobile = 1;
- dinfo->pll_index = PLLS_I9xx;
- return 0;
- default:
- return 1;
- }
-}
-
-int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
- int *stolen_size)
-{
- struct pci_dev *bridge_dev;
- u16 tmp;
- int stolen_overhead;
-
- if (!pdev || !aperture_size || !stolen_size)
- return 1;
-
- /* Find the bridge device. It is always 0:0.0 */
- bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
- PCI_DEVFN(0, 0));
- if (!bridge_dev) {
- ERR_MSG("cannot find bridge device\n");
- return 1;
- }
-
- /* Get the fb aperture size and "stolen" memory amount. */
- tmp = 0;
- pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
- pci_dev_put(bridge_dev);
-
- switch (pdev->device) {
- case PCI_DEVICE_ID_INTEL_915G:
- case PCI_DEVICE_ID_INTEL_915GM:
- case PCI_DEVICE_ID_INTEL_945G:
- case PCI_DEVICE_ID_INTEL_945GM:
- case PCI_DEVICE_ID_INTEL_945GME:
- case PCI_DEVICE_ID_INTEL_965G:
- case PCI_DEVICE_ID_INTEL_965GM:
- /*
- * 915, 945 and 965 chipsets support 64MB, 128MB or 256MB
- * aperture. Determine size from PCI resource length.
- */
- *aperture_size = pci_resource_len(pdev, 2);
- break;
- default:
- if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
- *aperture_size = MB(64);
- else
- *aperture_size = MB(128);
- break;
- }
-
- /* Stolen memory size is reduced by the GTT and the popup.
- GTT is 1K per MB of aperture size, and popup is 4K. */
- stolen_overhead = (*aperture_size / MB(1)) + 4;
- switch(pdev->device) {
- case PCI_DEVICE_ID_INTEL_830M:
- case PCI_DEVICE_ID_INTEL_845G:
- switch (tmp & INTEL_830_GMCH_GMS_MASK) {
- case INTEL_830_GMCH_GMS_STOLEN_512:
- *stolen_size = KB(512) - KB(stolen_overhead);
- return 0;
- case INTEL_830_GMCH_GMS_STOLEN_1024:
- *stolen_size = MB(1) - KB(stolen_overhead);
- return 0;
- case INTEL_830_GMCH_GMS_STOLEN_8192:
- *stolen_size = MB(8) - KB(stolen_overhead);
- return 0;
- case INTEL_830_GMCH_GMS_LOCAL:
- ERR_MSG("only local memory found\n");
- return 1;
- case INTEL_830_GMCH_GMS_DISABLED:
- ERR_MSG("video memory is disabled\n");
- return 1;
- default:
- ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
- tmp & INTEL_830_GMCH_GMS_MASK);
- return 1;
- }
- break;
- default:
- switch (tmp & INTEL_855_GMCH_GMS_MASK) {
- case INTEL_855_GMCH_GMS_STOLEN_1M:
- *stolen_size = MB(1) - KB(stolen_overhead);
- return 0;
- case INTEL_855_GMCH_GMS_STOLEN_4M:
- *stolen_size = MB(4) - KB(stolen_overhead);
- return 0;
- case INTEL_855_GMCH_GMS_STOLEN_8M:
- *stolen_size = MB(8) - KB(stolen_overhead);
- return 0;
- case INTEL_855_GMCH_GMS_STOLEN_16M:
- *stolen_size = MB(16) - KB(stolen_overhead);
- return 0;
- case INTEL_855_GMCH_GMS_STOLEN_32M:
- *stolen_size = MB(32) - KB(stolen_overhead);
- return 0;
- case INTEL_915G_GMCH_GMS_STOLEN_48M:
- *stolen_size = MB(48) - KB(stolen_overhead);
- return 0;
- case INTEL_915G_GMCH_GMS_STOLEN_64M:
- *stolen_size = MB(64) - KB(stolen_overhead);
- return 0;
- case INTEL_855_GMCH_GMS_DISABLED:
- ERR_MSG("video memory is disabled\n");
- return 0;
- default:
- ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
- tmp & INTEL_855_GMCH_GMS_MASK);
- return 1;
- }
- }
-}
-
-int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
-{
- int dvo = 0;
-
- if (INREG(LVDS) & PORT_ENABLE)
- dvo |= LVDS_PORT;
- if (INREG(DVOA) & PORT_ENABLE)
- dvo |= DVOA_PORT;
- if (INREG(DVOB) & PORT_ENABLE)
- dvo |= DVOB_PORT;
- if (INREG(DVOC) & PORT_ENABLE)
- dvo |= DVOC_PORT;
-
- return dvo;
-}
-
-const char * intelfbhw_dvo_to_string(int dvo)
-{
- if (dvo & DVOA_PORT)
- return "DVO port A";
- else if (dvo & DVOB_PORT)
- return "DVO port B";
- else if (dvo & DVOC_PORT)
- return "DVO port C";
- else if (dvo & LVDS_PORT)
- return "LVDS port";
- else
- return NULL;
-}
-
-
-int intelfbhw_validate_mode(struct intelfb_info *dinfo,
- struct fb_var_screeninfo *var)
-{
- int bytes_per_pixel;
- int tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_validate_mode\n");
-#endif
-
- bytes_per_pixel = var->bits_per_pixel / 8;
- if (bytes_per_pixel == 3)
- bytes_per_pixel = 4;
-
- /* Check if enough video memory. */
- tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
- if (tmp > dinfo->fb.size) {
- WRN_MSG("Not enough video ram for mode "
- "(%d KByte vs %d KByte).\n",
- BtoKB(tmp), BtoKB(dinfo->fb.size));
- return 1;
- }
-
- /* Check if x/y limits are OK. */
- if (var->xres - 1 > HACTIVE_MASK) {
- WRN_MSG("X resolution too large (%d vs %d).\n",
- var->xres, HACTIVE_MASK + 1);
- return 1;
- }
- if (var->yres - 1 > VACTIVE_MASK) {
- WRN_MSG("Y resolution too large (%d vs %d).\n",
- var->yres, VACTIVE_MASK + 1);
- return 1;
- }
- if (var->xres < 4) {
- WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);
- return 1;
- }
- if (var->yres < 4) {
- WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);
- return 1;
- }
-
- /* Check for doublescan modes. */
- if (var->vmode & FB_VMODE_DOUBLE) {
- WRN_MSG("Mode is double-scan.\n");
- return 1;
- }
-
- if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {
- WRN_MSG("Odd number of lines in interlaced mode\n");
- return 1;
- }
-
- /* Check if clock is OK. */
- tmp = 1000000000 / var->pixclock;
- if (tmp < MIN_CLOCK) {
- WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
- (tmp + 500) / 1000, MIN_CLOCK / 1000);
- return 1;
- }
- if (tmp > MAX_CLOCK) {
- WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
- (tmp + 500) / 1000, MAX_CLOCK / 1000);
- return 1;
- }
-
- return 0;
-}
-
-int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 offset, xoffset, yoffset;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_pan_display\n");
-#endif
-
- xoffset = ROUND_DOWN_TO(var->xoffset, 8);
- yoffset = var->yoffset;
-
- if ((xoffset + info->var.xres > info->var.xres_virtual) ||
- (yoffset + info->var.yres > info->var.yres_virtual))
- return -EINVAL;
-
- offset = (yoffset * dinfo->pitch) +
- (xoffset * info->var.bits_per_pixel) / 8;
-
- offset += dinfo->fb.offset << 12;
-
- dinfo->vsync.pan_offset = offset;
- if ((var->activate & FB_ACTIVATE_VBL) &&
- !intelfbhw_enable_irq(dinfo))
- dinfo->vsync.pan_display = 1;
- else {
- dinfo->vsync.pan_display = 0;
- OUTREG(DSPABASE, offset);
- }
-
- return 0;
-}
-
-/* Blank the screen. */
-void intelfbhw_do_blank(int blank, struct fb_info *info)
-{
- struct intelfb_info *dinfo = GET_DINFO(info);
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
-#endif
-
- /* Turn plane A on or off */
- tmp = INREG(DSPACNTR);
- if (blank)
- tmp &= ~DISPPLANE_PLANE_ENABLE;
- else
- tmp |= DISPPLANE_PLANE_ENABLE;
- OUTREG(DSPACNTR, tmp);
- /* Flush */
- tmp = INREG(DSPABASE);
- OUTREG(DSPABASE, tmp);
-
- /* Turn off/on the HW cursor */
-#if VERBOSE > 0
- DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
-#endif
- if (dinfo->cursor_on) {
- if (blank)
- intelfbhw_cursor_hide(dinfo);
- else
- intelfbhw_cursor_show(dinfo);
- dinfo->cursor_on = 1;
- }
- dinfo->cursor_blanked = blank;
-
- /* Set DPMS level */
- tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
- switch (blank) {
- case FB_BLANK_UNBLANK:
- case FB_BLANK_NORMAL:
- tmp |= ADPA_DPMS_D0;
- break;
- case FB_BLANK_VSYNC_SUSPEND:
- tmp |= ADPA_DPMS_D1;
- break;
- case FB_BLANK_HSYNC_SUSPEND:
- tmp |= ADPA_DPMS_D2;
- break;
- case FB_BLANK_POWERDOWN:
- tmp |= ADPA_DPMS_D3;
- break;
- }
- OUTREG(ADPA, tmp);
-
- return;
-}
-
-
-/* Check which pipe is connected to an active display plane. */
-int intelfbhw_active_pipe(const struct intelfb_hwstate *hw)
-{
- int pipe = -1;
-
- /* keep old default behaviour - prefer PIPE_A */
- if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) {
- pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
- pipe &= PIPE_MASK;
- if (unlikely(pipe == PIPE_A))
- return PIPE_A;
- }
- if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) {
- pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
- pipe &= PIPE_MASK;
- if (likely(pipe == PIPE_A))
- return PIPE_A;
- }
- /* Impossible that no pipe is selected - return PIPE_A */
- WARN_ON(pipe == -1);
- if (unlikely(pipe == -1))
- pipe = PIPE_A;
-
- return pipe;
-}
-
-void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
- unsigned red, unsigned green, unsigned blue,
- unsigned transp)
-{
- u32 palette_reg = (dinfo->pipe == PIPE_A) ?
- PALETTE_A : PALETTE_B;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
- regno, red, green, blue);
-#endif
-
- OUTREG(palette_reg + (regno << 2),
- (red << PALETTE_8_RED_SHIFT) |
- (green << PALETTE_8_GREEN_SHIFT) |
- (blue << PALETTE_8_BLUE_SHIFT));
-}
-
-
-int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw, int flag)
-{
- int i;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_read_hw_state\n");
-#endif
-
- if (!hw || !dinfo)
- return -1;
-
- /* Read in as much of the HW state as possible. */
- hw->vga0_divisor = INREG(VGA0_DIVISOR);
- hw->vga1_divisor = INREG(VGA1_DIVISOR);
- hw->vga_pd = INREG(VGAPD);
- hw->dpll_a = INREG(DPLL_A);
- hw->dpll_b = INREG(DPLL_B);
- hw->fpa0 = INREG(FPA0);
- hw->fpa1 = INREG(FPA1);
- hw->fpb0 = INREG(FPB0);
- hw->fpb1 = INREG(FPB1);
-
- if (flag == 1)
- return flag;
-
-#if 0
- /* This seems to be a problem with the 852GM/855GM */
- for (i = 0; i < PALETTE_8_ENTRIES; i++) {
- hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
- hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
- }
-#endif
-
- if (flag == 2)
- return flag;
-
- hw->htotal_a = INREG(HTOTAL_A);
- hw->hblank_a = INREG(HBLANK_A);
- hw->hsync_a = INREG(HSYNC_A);
- hw->vtotal_a = INREG(VTOTAL_A);
- hw->vblank_a = INREG(VBLANK_A);
- hw->vsync_a = INREG(VSYNC_A);
- hw->src_size_a = INREG(SRC_SIZE_A);
- hw->bclrpat_a = INREG(BCLRPAT_A);
- hw->htotal_b = INREG(HTOTAL_B);
- hw->hblank_b = INREG(HBLANK_B);
- hw->hsync_b = INREG(HSYNC_B);
- hw->vtotal_b = INREG(VTOTAL_B);
- hw->vblank_b = INREG(VBLANK_B);
- hw->vsync_b = INREG(VSYNC_B);
- hw->src_size_b = INREG(SRC_SIZE_B);
- hw->bclrpat_b = INREG(BCLRPAT_B);
-
- if (flag == 3)
- return flag;
-
- hw->adpa = INREG(ADPA);
- hw->dvoa = INREG(DVOA);
- hw->dvob = INREG(DVOB);
- hw->dvoc = INREG(DVOC);
- hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
- hw->dvob_srcdim = INREG(DVOB_SRCDIM);
- hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
- hw->lvds = INREG(LVDS);
-
- if (flag == 4)
- return flag;
-
- hw->pipe_a_conf = INREG(PIPEACONF);
- hw->pipe_b_conf = INREG(PIPEBCONF);
- hw->disp_arb = INREG(DISPARB);
-
- if (flag == 5)
- return flag;
-
- hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
- hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
- hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
- hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
-
- if (flag == 6)
- return flag;
-
- for (i = 0; i < 4; i++) {
- hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
- hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
- }
-
- if (flag == 7)
- return flag;
-
- hw->cursor_size = INREG(CURSOR_SIZE);
-
- if (flag == 8)
- return flag;
-
- hw->disp_a_ctrl = INREG(DSPACNTR);
- hw->disp_b_ctrl = INREG(DSPBCNTR);
- hw->disp_a_base = INREG(DSPABASE);
- hw->disp_b_base = INREG(DSPBBASE);
- hw->disp_a_stride = INREG(DSPASTRIDE);
- hw->disp_b_stride = INREG(DSPBSTRIDE);
-
- if (flag == 9)
- return flag;
-
- hw->vgacntrl = INREG(VGACNTRL);
-
- if (flag == 10)
- return flag;
-
- hw->add_id = INREG(ADD_ID);
-
- if (flag == 11)
- return flag;
-
- for (i = 0; i < 7; i++) {
- hw->swf0x[i] = INREG(SWF00 + (i << 2));
- hw->swf1x[i] = INREG(SWF10 + (i << 2));
- if (i < 3)
- hw->swf3x[i] = INREG(SWF30 + (i << 2));
- }
-
- for (i = 0; i < 8; i++)
- hw->fence[i] = INREG(FENCE + (i << 2));
-
- hw->instpm = INREG(INSTPM);
- hw->mem_mode = INREG(MEM_MODE);
- hw->fw_blc_0 = INREG(FW_BLC_0);
- hw->fw_blc_1 = INREG(FW_BLC_1);
-
- hw->hwstam = INREG16(HWSTAM);
- hw->ier = INREG16(IER);
- hw->iir = INREG16(IIR);
- hw->imr = INREG16(IMR);
-
- return 0;
-}
-
-
-static int calc_vclock3(int index, int m, int n, int p)
-{
- if (p == 0 || n == 0)
- return 0;
- return plls[index].ref_clk * m / n / p;
-}
-
-static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
- int lvds)
-{
- struct pll_min_max *pll = &plls[index];
- u32 m, vco, p;
-
- m = (5 * (m1 + 2)) + (m2 + 2);
- n += 2;
- vco = pll->ref_clk * m / n;
-
- if (index == PLLS_I8xx)
- p = ((p1 + 2) * (1 << (p2 + 1)));
- else
- p = ((p1) * (p2 ? 5 : 10));
- return vco / p;
-}
-
-#if REGDUMP
-static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
- int *o_p1, int *o_p2)
-{
- int p1, p2;
-
- if (IS_I9XX(dinfo)) {
- if (dpll & DPLL_P1_FORCE_DIV2)
- p1 = 1;
- else
- p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
-
- p1 = ffs(p1);
-
- p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
- } else {
- if (dpll & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
- }
-
- *o_p1 = p1;
- *o_p2 = p2;
-}
-#endif
-
-
-void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw)
-{
-#if REGDUMP
- int i, m1, m2, n, p1, p2;
- int index = dinfo->pll_index;
- DBG_MSG("intelfbhw_print_hw_state\n");
-
- if (!hw)
- return;
- /* Read in as much of the HW state as possible. */
- printk("hw state dump start\n");
- printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
- printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
- printk(" VGAPD: 0x%08x\n", hw->vga_pd);
- n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
-
- intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
-
- printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" VGA0: clock is %d\n",
- calc_vclock(index, m1, m2, n, p1, p2, 0));
-
- n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
-
- intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
- printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" VGA1: clock is %d\n",
- calc_vclock(index, m1, m2, n, p1, p2, 0));
-
- printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
- printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
- printk(" FPA0: 0x%08x\n", hw->fpa0);
- printk(" FPA1: 0x%08x\n", hw->fpa1);
- printk(" FPB0: 0x%08x\n", hw->fpb0);
- printk(" FPB1: 0x%08x\n", hw->fpb1);
-
- n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
-
- intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
-
- printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" PLLA0: clock is %d\n",
- calc_vclock(index, m1, m2, n, p1, p2, 0));
-
- n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
-
- intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
-
- printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" PLLA1: clock is %d\n",
- calc_vclock(index, m1, m2, n, p1, p2, 0));
-
-#if 0
- printk(" PALETTE_A:\n");
- for (i = 0; i < PALETTE_8_ENTRIES)
- printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
- printk(" PALETTE_B:\n");
- for (i = 0; i < PALETTE_8_ENTRIES)
- printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
-#endif
-
- printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
- printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
- printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
- printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
- printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
- printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
- printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
- printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
- printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
- printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
- printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
- printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
- printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
- printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
- printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
- printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
-
- printk(" ADPA: 0x%08x\n", hw->adpa);
- printk(" DVOA: 0x%08x\n", hw->dvoa);
- printk(" DVOB: 0x%08x\n", hw->dvob);
- printk(" DVOC: 0x%08x\n", hw->dvoc);
- printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
- printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
- printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
- printk(" LVDS: 0x%08x\n", hw->lvds);
-
- printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
- printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
- printk(" DISPARB: 0x%08x\n", hw->disp_arb);
-
- printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
- printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
- printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
- printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
-
- printk(" CURSOR_A_PALETTE: ");
- for (i = 0; i < 4; i++) {
- printk("0x%08x", hw->cursor_a_palette[i]);
- if (i < 3)
- printk(", ");
- }
- printk("\n");
- printk(" CURSOR_B_PALETTE: ");
- for (i = 0; i < 4; i++) {
- printk("0x%08x", hw->cursor_b_palette[i]);
- if (i < 3)
- printk(", ");
- }
- printk("\n");
-
- printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
-
- printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
- printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
- printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
- printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
- printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
- printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
-
- printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
- printk(" ADD_ID: 0x%08x\n", hw->add_id);
-
- for (i = 0; i < 7; i++) {
- printk(" SWF0%d 0x%08x\n", i,
- hw->swf0x[i]);
- }
- for (i = 0; i < 7; i++) {
- printk(" SWF1%d 0x%08x\n", i,
- hw->swf1x[i]);
- }
- for (i = 0; i < 3; i++) {
- printk(" SWF3%d 0x%08x\n", i,
- hw->swf3x[i]);
- }
- for (i = 0; i < 8; i++)
- printk(" FENCE%d 0x%08x\n", i,
- hw->fence[i]);
-
- printk(" INSTPM 0x%08x\n", hw->instpm);
- printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
- printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
- printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
-
- printk(" HWSTAM 0x%04x\n", hw->hwstam);
- printk(" IER 0x%04x\n", hw->ier);
- printk(" IIR 0x%04x\n", hw->iir);
- printk(" IMR 0x%04x\n", hw->imr);
- printk("hw state dump end\n");
-#endif
-}
-
-
-
-/* Split the M parameter into M1 and M2. */
-static int splitm(int index, unsigned int m, unsigned int *retm1,
- unsigned int *retm2)
-{
- int m1, m2;
- int testm;
- struct pll_min_max *pll = &plls[index];
-
- /* no point optimising too much - brute force m */
- for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
- for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
- testm = (5 * (m1 + 2)) + (m2 + 2);
- if (testm == m) {
- *retm1 = (unsigned int)m1;
- *retm2 = (unsigned int)m2;
- return 0;
- }
- }
- }
- return 1;
-}
-
-/* Split the P parameter into P1 and P2. */
-static int splitp(int index, unsigned int p, unsigned int *retp1,
- unsigned int *retp2)
-{
- int p1, p2;
- struct pll_min_max *pll = &plls[index];
-
- if (index == PLLS_I9xx) {
- p2 = (p % 10) ? 1 : 0;
-
- p1 = p / (p2 ? 5 : 10);
-
- *retp1 = (unsigned int)p1;
- *retp2 = (unsigned int)p2;
- return 0;
- }
-
- if (p % 4 == 0)
- p2 = 1;
- else
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- if (p % 4 == 0 && p1 < pll->min_p1) {
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- }
- if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
- (p1 + 2) * (1 << (p2 + 1)) != p) {
- return 1;
- } else {
- *retp1 = (unsigned int)p1;
- *retp2 = (unsigned int)p2;
- return 0;
- }
-}
-
-static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
- u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
-{
- u32 m1, m2, n, p1, p2, n1, testm;
- u32 f_vco, p, p_best = 0, m, f_out = 0;
- u32 err_best = 10000000;
- u32 n_best = 0, m_best = 0, f_err;
- u32 p_min, p_max, p_inc, div_max;
- struct pll_min_max *pll = &plls[index];
-
- DBG_MSG("Clock is %d\n", clock);
-
- div_max = pll->max_vco / clock;
-
- p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
- p_min = p_inc;
- p_max = ROUND_DOWN_TO(div_max, p_inc);
- if (p_min < pll->min_p)
- p_min = pll->min_p;
- if (p_max > pll->max_p)
- p_max = pll->max_p;
-
- DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
-
- p = p_min;
- do {
- if (splitp(index, p, &p1, &p2)) {
- WRN_MSG("cannot split p = %d\n", p);
- p += p_inc;
- continue;
- }
- n = pll->min_n;
- f_vco = clock * p;
-
- do {
- m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
- if (m < pll->min_m)
- m = pll->min_m + 1;
- if (m > pll->max_m)
- m = pll->max_m - 1;
- for (testm = m - 1; testm <= m; testm++) {
- f_out = calc_vclock3(index, testm, n, p);
- if (splitm(index, testm, &m1, &m2)) {
- WRN_MSG("cannot split m = %d\n",
- testm);
- continue;
- }
- if (clock > f_out)
- f_err = clock - f_out;
- else/* slightly bias the error for bigger clocks */
- f_err = f_out - clock + 1;
-
- if (f_err < err_best) {
- m_best = testm;
- n_best = n;
- p_best = p;
- err_best = f_err;
- }
- }
- n++;
- } while ((n <= pll->max_n) && (f_out >= clock));
- p += p_inc;
- } while ((p <= p_max));
-
- if (!m_best) {
- WRN_MSG("cannot find parameters for clock %d\n", clock);
- return 1;
- }
- m = m_best;
- n = n_best;
- p = p_best;
- splitm(index, m, &m1, &m2);
- splitp(index, p, &p1, &p2);
- n1 = n - 2;
-
- DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
- "f: %d (%d), VCO: %d\n",
- m, m1, m2, n, n1, p, p1, p2,
- calc_vclock3(index, m, n, p),
- calc_vclock(index, m1, m2, n1, p1, p2, 0),
- calc_vclock3(index, m, n, p) * p);
- *retm1 = m1;
- *retm2 = m2;
- *retn = n1;
- *retp1 = p1;
- *retp2 = p2;
- *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
-
- return 0;
-}
-
-static __inline__ int check_overflow(u32 value, u32 limit,
- const char *description)
-{
- if (value > limit) {
- WRN_MSG("%s value %d exceeds limit %d\n",
- description, value, limit);
- return 1;
- }
- return 0;
-}
-
-/* It is assumed that hw is filled in with the initial state information. */
-int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw,
- struct fb_var_screeninfo *var)
-{
- int pipe = intelfbhw_active_pipe(hw);
- u32 *dpll, *fp0, *fp1;
- u32 m1, m2, n, p1, p2, clock_target, clock;
- u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
- u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
- u32 vsync_pol, hsync_pol;
- u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
- u32 stride_alignment;
-
- DBG_MSG("intelfbhw_mode_to_hw\n");
-
- /* Disable VGA */
- hw->vgacntrl |= VGA_DISABLE;
-
- /* Set which pipe's registers will be set. */
- if (pipe == PIPE_B) {
- dpll = &hw->dpll_b;
- fp0 = &hw->fpb0;
- fp1 = &hw->fpb1;
- hs = &hw->hsync_b;
- hb = &hw->hblank_b;
- ht = &hw->htotal_b;
- vs = &hw->vsync_b;
- vb = &hw->vblank_b;
- vt = &hw->vtotal_b;
- ss = &hw->src_size_b;
- pipe_conf = &hw->pipe_b_conf;
- } else {
- dpll = &hw->dpll_a;
- fp0 = &hw->fpa0;
- fp1 = &hw->fpa1;
- hs = &hw->hsync_a;
- hb = &hw->hblank_a;
- ht = &hw->htotal_a;
- vs = &hw->vsync_a;
- vb = &hw->vblank_a;
- vt = &hw->vtotal_a;
- ss = &hw->src_size_a;
- pipe_conf = &hw->pipe_a_conf;
- }
-
- /* Use ADPA register for sync control. */
- hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
-
- /* sync polarity */
- hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
- ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
- vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
- ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
- hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
- (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
- hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
- (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
-
- /* Connect correct pipe to the analog port DAC */
- hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
- hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
-
- /* Set DPMS state to D0 (on) */
- hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
- hw->adpa |= ADPA_DPMS_D0;
-
- hw->adpa |= ADPA_DAC_ENABLE;
-
- *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
- *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
- *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
-
- /* Desired clock in kHz */
- clock_target = 1000000000 / var->pixclock;
-
- if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
- &n, &p1, &p2, &clock)) {
- WRN_MSG("calc_pll_params failed\n");
- return 1;
- }
-
- /* Check for overflow. */
- if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
- return 1;
- if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
- return 1;
- if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
- return 1;
- if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
- return 1;
- if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
- return 1;
-
- *dpll &= ~DPLL_P1_FORCE_DIV2;
- *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
- (DPLL_P1_MASK << DPLL_P1_SHIFT));
-
- if (IS_I9XX(dinfo)) {
- *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
- *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
- } else
- *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
-
- *fp0 = (n << FP_N_DIVISOR_SHIFT) |
- (m1 << FP_M1_DIVISOR_SHIFT) |
- (m2 << FP_M2_DIVISOR_SHIFT);
- *fp1 = *fp0;
-
- hw->dvob &= ~PORT_ENABLE;
- hw->dvoc &= ~PORT_ENABLE;
-
- /* Use display plane A. */
- hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
- hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
- hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
- switch (intelfb_var_to_depth(var)) {
- case 8:
- hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
- break;
- case 15:
- hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
- break;
- case 16:
- hw->disp_a_ctrl |= DISPPLANE_16BPP;
- break;
- case 24:
- hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
- break;
- }
- hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
- hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
-
- /* Set CRTC registers. */
- hactive = var->xres;
- hsync_start = hactive + var->right_margin;
- hsync_end = hsync_start + var->hsync_len;
- htotal = hsync_end + var->left_margin;
- hblank_start = hactive;
- hblank_end = htotal;
-
- DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
- hactive, hsync_start, hsync_end, htotal, hblank_start,
- hblank_end);
-
- vactive = var->yres;
- if (var->vmode & FB_VMODE_INTERLACED)
- vactive--; /* the chip adds 2 halflines automatically */
- vsync_start = vactive + var->lower_margin;
- vsync_end = vsync_start + var->vsync_len;
- vtotal = vsync_end + var->upper_margin;
- vblank_start = vactive;
- vblank_end = vsync_end + 1;
-
- DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
- vactive, vsync_start, vsync_end, vtotal, vblank_start,
- vblank_end);
-
- /* Adjust for register values, and check for overflow. */
- hactive--;
- if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
- return 1;
- hsync_start--;
- if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
- return 1;
- hsync_end--;
- if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
- return 1;
- htotal--;
- if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
- return 1;
- hblank_start--;
- if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
- return 1;
- hblank_end--;
- if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
- return 1;
-
- vactive--;
- if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
- return 1;
- vsync_start--;
- if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
- return 1;
- vsync_end--;
- if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
- return 1;
- vtotal--;
- if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
- return 1;
- vblank_start--;
- if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
- return 1;
- vblank_end--;
- if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
- return 1;
-
- *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
- *hb = (hblank_start << HBLANKSTART_SHIFT) |
- (hblank_end << HSYNCEND_SHIFT);
- *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
-
- *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
- *vb = (vblank_start << VBLANKSTART_SHIFT) |
- (vblank_end << VSYNCEND_SHIFT);
- *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
- *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
- (vactive << SRC_SIZE_VERT_SHIFT);
-
- hw->disp_a_stride = dinfo->pitch;
- DBG_MSG("pitch is %d\n", hw->disp_a_stride);
-
- hw->disp_a_base = hw->disp_a_stride * var->yoffset +
- var->xoffset * var->bits_per_pixel / 8;
-
- hw->disp_a_base += dinfo->fb.offset << 12;
-
- /* Check stride alignment. */
- stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
- STRIDE_ALIGNMENT;
- if (hw->disp_a_stride % stride_alignment != 0) {
- WRN_MSG("display stride %d has bad alignment %d\n",
- hw->disp_a_stride, stride_alignment);
- return 1;
- }
-
- /* Set the palette to 8-bit mode. */
- *pipe_conf &= ~PIPECONF_GAMMA;
-
- if (var->vmode & FB_VMODE_INTERLACED)
- *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
- else
- *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
-
- return 0;
-}
-
-/* Program a (non-VGA) video mode. */
-int intelfbhw_program_mode(struct intelfb_info *dinfo,
- const struct intelfb_hwstate *hw, int blank)
-{
- u32 tmp;
- const u32 *dpll, *fp0, *fp1, *pipe_conf;
- const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
- u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
- u32 hsync_reg, htotal_reg, hblank_reg;
- u32 vsync_reg, vtotal_reg, vblank_reg;
- u32 src_size_reg;
- u32 count, tmp_val[3];
-
- /* Assume single pipe */
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_program_mode\n");
-#endif
-
- /* Disable VGA */
- tmp = INREG(VGACNTRL);
- tmp |= VGA_DISABLE;
- OUTREG(VGACNTRL, tmp);
-
- dinfo->pipe = intelfbhw_active_pipe(hw);
-
- if (dinfo->pipe == PIPE_B) {
- dpll = &hw->dpll_b;
- fp0 = &hw->fpb0;
- fp1 = &hw->fpb1;
- pipe_conf = &hw->pipe_b_conf;
- hs = &hw->hsync_b;
- hb = &hw->hblank_b;
- ht = &hw->htotal_b;
- vs = &hw->vsync_b;
- vb = &hw->vblank_b;
- vt = &hw->vtotal_b;
- ss = &hw->src_size_b;
- dpll_reg = DPLL_B;
- fp0_reg = FPB0;
- fp1_reg = FPB1;
- pipe_conf_reg = PIPEBCONF;
- pipe_stat_reg = PIPEBSTAT;
- hsync_reg = HSYNC_B;
- htotal_reg = HTOTAL_B;
- hblank_reg = HBLANK_B;
- vsync_reg = VSYNC_B;
- vtotal_reg = VTOTAL_B;
- vblank_reg = VBLANK_B;
- src_size_reg = SRC_SIZE_B;
- } else {
- dpll = &hw->dpll_a;
- fp0 = &hw->fpa0;
- fp1 = &hw->fpa1;
- pipe_conf = &hw->pipe_a_conf;
- hs = &hw->hsync_a;
- hb = &hw->hblank_a;
- ht = &hw->htotal_a;
- vs = &hw->vsync_a;
- vb = &hw->vblank_a;
- vt = &hw->vtotal_a;
- ss = &hw->src_size_a;
- dpll_reg = DPLL_A;
- fp0_reg = FPA0;
- fp1_reg = FPA1;
- pipe_conf_reg = PIPEACONF;
- pipe_stat_reg = PIPEASTAT;
- hsync_reg = HSYNC_A;
- htotal_reg = HTOTAL_A;
- hblank_reg = HBLANK_A;
- vsync_reg = VSYNC_A;
- vtotal_reg = VTOTAL_A;
- vblank_reg = VBLANK_A;
- src_size_reg = SRC_SIZE_A;
- }
-
- /* turn off pipe */
- tmp = INREG(pipe_conf_reg);
- tmp &= ~PIPECONF_ENABLE;
- OUTREG(pipe_conf_reg, tmp);
-
- count = 0;
- do {
- tmp_val[count % 3] = INREG(PIPEA_DSL);
- if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
- break;
- count++;
- udelay(1);
- if (count % 200 == 0) {
- tmp = INREG(pipe_conf_reg);
- tmp &= ~PIPECONF_ENABLE;
- OUTREG(pipe_conf_reg, tmp);
- }
- } while (count < 2000);
-
- OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
-
- /* Disable planes A and B. */
- tmp = INREG(DSPACNTR);
- tmp &= ~DISPPLANE_PLANE_ENABLE;
- OUTREG(DSPACNTR, tmp);
- tmp = INREG(DSPBCNTR);
- tmp &= ~DISPPLANE_PLANE_ENABLE;
- OUTREG(DSPBCNTR, tmp);
-
- /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
- mdelay(20);
-
- OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
- OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
- OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
-
- /* Disable Sync */
- tmp = INREG(ADPA);
- tmp &= ~ADPA_DPMS_CONTROL_MASK;
- tmp |= ADPA_DPMS_D3;
- OUTREG(ADPA, tmp);
-
- /* do some funky magic - xyzzy */
- OUTREG(0x61204, 0xabcd0000);
-
- /* turn off PLL */
- tmp = INREG(dpll_reg);
- tmp &= ~DPLL_VCO_ENABLE;
- OUTREG(dpll_reg, tmp);
-
- /* Set PLL parameters */
- OUTREG(fp0_reg, *fp0);
- OUTREG(fp1_reg, *fp1);
-
- /* Enable PLL */
- OUTREG(dpll_reg, *dpll);
-
- /* Set DVOs B/C */
- OUTREG(DVOB, hw->dvob);
- OUTREG(DVOC, hw->dvoc);
-
- /* undo funky magic */
- OUTREG(0x61204, 0x00000000);
-
- /* Set ADPA */
- OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
- OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
-
- /* Set pipe parameters */
- OUTREG(hsync_reg, *hs);
- OUTREG(hblank_reg, *hb);
- OUTREG(htotal_reg, *ht);
- OUTREG(vsync_reg, *vs);
- OUTREG(vblank_reg, *vb);
- OUTREG(vtotal_reg, *vt);
- OUTREG(src_size_reg, *ss);
-
- switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
- FB_VMODE_ODD_FLD_FIRST)) {
- case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
- OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
- break;
- case FB_VMODE_INTERLACED: /* even lines first */
- OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
- break;
- default: /* non-interlaced */
- OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
- }
- /* Enable pipe */
- OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
-
- /* Enable sync */
- tmp = INREG(ADPA);
- tmp &= ~ADPA_DPMS_CONTROL_MASK;
- tmp |= ADPA_DPMS_D0;
- OUTREG(ADPA, tmp);
-
- /* setup display plane */
- if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
- /*
- * i830M errata: the display plane must be enabled
- * to allow writes to the other bits in the plane
- * control register.
- */
- tmp = INREG(DSPACNTR);
- if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
- tmp |= DISPPLANE_PLANE_ENABLE;
- OUTREG(DSPACNTR, tmp);
- OUTREG(DSPACNTR,
- hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
- mdelay(1);
- }
- }
-
- OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
- OUTREG(DSPASTRIDE, hw->disp_a_stride);
- OUTREG(DSPABASE, hw->disp_a_base);
-
- /* Enable plane */
- if (!blank) {
- tmp = INREG(DSPACNTR);
- tmp |= DISPPLANE_PLANE_ENABLE;
- OUTREG(DSPACNTR, tmp);
- OUTREG(DSPABASE, hw->disp_a_base);
- }
-
- return 0;
-}
-
-/* forward declarations */
-static void refresh_ring(struct intelfb_info *dinfo);
-static void reset_state(struct intelfb_info *dinfo);
-static void do_flush(struct intelfb_info *dinfo);
-
-static u32 get_ring_space(struct intelfb_info *dinfo)
-{
- u32 ring_space;
-
- if (dinfo->ring_tail >= dinfo->ring_head)
- ring_space = dinfo->ring.size -
- (dinfo->ring_tail - dinfo->ring_head);
- else
- ring_space = dinfo->ring_head - dinfo->ring_tail;
-
- if (ring_space > RING_MIN_FREE)
- ring_space -= RING_MIN_FREE;
- else
- ring_space = 0;
-
- return ring_space;
-}
-
-static int wait_ring(struct intelfb_info *dinfo, int n)
-{
- int i = 0;
- unsigned long end;
- u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
-
-#if VERBOSE > 0
- DBG_MSG("wait_ring: %d\n", n);
-#endif
-
- end = jiffies + (HZ * 3);
- while (dinfo->ring_space < n) {
- dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
- dinfo->ring_space = get_ring_space(dinfo);
-
- if (dinfo->ring_head != last_head) {
- end = jiffies + (HZ * 3);
- last_head = dinfo->ring_head;
- }
- i++;
- if (time_before(end, jiffies)) {
- if (!i) {
- /* Try again */
- reset_state(dinfo);
- refresh_ring(dinfo);
- do_flush(dinfo);
- end = jiffies + (HZ * 3);
- i = 1;
- } else {
- WRN_MSG("ring buffer : space: %d wanted %d\n",
- dinfo->ring_space, n);
- WRN_MSG("lockup - turning off hardware "
- "acceleration\n");
- dinfo->ring_lockup = 1;
- break;
- }
- }
- udelay(1);
- }
- return i;
-}
-
-static void do_flush(struct intelfb_info *dinfo)
-{
- START_RING(2);
- OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
- OUT_RING(MI_NOOP);
- ADVANCE_RING();
-}
-
-void intelfbhw_do_sync(struct intelfb_info *dinfo)
-{
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_do_sync\n");
-#endif
-
- if (!dinfo->accel)
- return;
-
- /*
- * Send a flush, then wait until the ring is empty. This is what
- * the XFree86 driver does, and actually it doesn't seem a lot worse
- * than the recommended method (both have problems).
- */
- do_flush(dinfo);
- wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
- dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
-}
-
-static void refresh_ring(struct intelfb_info *dinfo)
-{
-#if VERBOSE > 0
- DBG_MSG("refresh_ring\n");
-#endif
-
- dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
- dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
- dinfo->ring_space = get_ring_space(dinfo);
-}
-
-static void reset_state(struct intelfb_info *dinfo)
-{
- int i;
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("reset_state\n");
-#endif
-
- for (i = 0; i < FENCE_NUM; i++)
- OUTREG(FENCE + (i << 2), 0);
-
- /* Flush the ring buffer if it's enabled. */
- tmp = INREG(PRI_RING_LENGTH);
- if (tmp & RING_ENABLE) {
-#if VERBOSE > 0
- DBG_MSG("reset_state: ring was enabled\n");
-#endif
- refresh_ring(dinfo);
- intelfbhw_do_sync(dinfo);
- DO_RING_IDLE();
- }
-
- OUTREG(PRI_RING_LENGTH, 0);
- OUTREG(PRI_RING_HEAD, 0);
- OUTREG(PRI_RING_TAIL, 0);
- OUTREG(PRI_RING_START, 0);
-}
-
-/* Stop the 2D engine, and turn off the ring buffer. */
-void intelfbhw_2d_stop(struct intelfb_info *dinfo)
-{
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
- dinfo->accel, dinfo->ring_active);
-#endif
-
- if (!dinfo->accel)
- return;
-
- dinfo->ring_active = 0;
- reset_state(dinfo);
-}
-
-/*
- * Enable the ring buffer, and initialise the 2D engine.
- * It is assumed that the graphics engine has been stopped by previously
- * calling intelfb_2d_stop().
- */
-void intelfbhw_2d_start(struct intelfb_info *dinfo)
-{
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
- dinfo->accel, dinfo->ring_active);
-#endif
-
- if (!dinfo->accel)
- return;
-
- /* Initialise the primary ring buffer. */
- OUTREG(PRI_RING_LENGTH, 0);
- OUTREG(PRI_RING_TAIL, 0);
- OUTREG(PRI_RING_HEAD, 0);
-
- OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
- OUTREG(PRI_RING_LENGTH,
- ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
- RING_NO_REPORT | RING_ENABLE);
- refresh_ring(dinfo);
- dinfo->ring_active = 1;
-}
-
-/* 2D fillrect (solid fill or invert) */
-void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
- u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
-{
- u32 br00, br09, br13, br14, br16;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
- "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
-#endif
-
- br00 = COLOR_BLT_CMD;
- br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
- br13 = (rop << ROP_SHIFT) | pitch;
- br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
- br16 = color;
-
- switch (bpp) {
- case 8:
- br13 |= COLOR_DEPTH_8;
- break;
- case 16:
- br13 |= COLOR_DEPTH_16;
- break;
- case 32:
- br13 |= COLOR_DEPTH_32;
- br00 |= WRITE_ALPHA | WRITE_RGB;
- break;
- }
-
- START_RING(6);
- OUT_RING(br00);
- OUT_RING(br13);
- OUT_RING(br14);
- OUT_RING(br09);
- OUT_RING(br16);
- OUT_RING(MI_NOOP);
- ADVANCE_RING();
-
-#if VERBOSE > 0
- DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
- dinfo->ring_tail, dinfo->ring_space);
-#endif
-}
-
-void
-intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
- u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
-{
- u32 br00, br09, br11, br12, br13, br22, br23, br26;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
- curx, cury, dstx, dsty, w, h, pitch, bpp);
-#endif
-
- br00 = XY_SRC_COPY_BLT_CMD;
- br09 = dinfo->fb_start;
- br11 = (pitch << PITCH_SHIFT);
- br12 = dinfo->fb_start;
- br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
- br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
- br23 = ((dstx + w) << WIDTH_SHIFT) |
- ((dsty + h) << HEIGHT_SHIFT);
- br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
-
- switch (bpp) {
- case 8:
- br13 |= COLOR_DEPTH_8;
- break;
- case 16:
- br13 |= COLOR_DEPTH_16;
- break;
- case 32:
- br13 |= COLOR_DEPTH_32;
- br00 |= WRITE_ALPHA | WRITE_RGB;
- break;
- }
-
- START_RING(8);
- OUT_RING(br00);
- OUT_RING(br13);
- OUT_RING(br22);
- OUT_RING(br23);
- OUT_RING(br09);
- OUT_RING(br26);
- OUT_RING(br11);
- OUT_RING(br12);
- ADVANCE_RING();
-}
-
-int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
- u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
- u32 bpp)
-{
- int nbytes, ndwords, pad, tmp;
- u32 br00, br09, br13, br18, br19, br22, br23;
- int dat, ix, iy, iw;
- int i, j;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
-#endif
-
- /* size in bytes of a padded scanline */
- nbytes = ROUND_UP_TO(w, 16) / 8;
-
- /* Total bytes of padded scanline data to write out. */
- nbytes = nbytes * h;
-
- /*
- * Check if the glyph data exceeds the immediate mode limit.
- * It would take a large font (1K pixels) to hit this limit.
- */
- if (nbytes > MAX_MONO_IMM_SIZE)
- return 0;
-
- /* Src data is packaged a dword (32-bit) at a time. */
- ndwords = ROUND_UP_TO(nbytes, 4) / 4;
-
- /*
- * Ring has to be padded to a quad word. But because the command starts
- with 7 bytes, pad only if there is an even number of ndwords
- */
- pad = !(ndwords % 2);
-
- tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
- br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
- br09 = dinfo->fb_start;
- br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
- br18 = bg;
- br19 = fg;
- br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
- br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
-
- switch (bpp) {
- case 8:
- br13 |= COLOR_DEPTH_8;
- break;
- case 16:
- br13 |= COLOR_DEPTH_16;
- break;
- case 32:
- br13 |= COLOR_DEPTH_32;
- br00 |= WRITE_ALPHA | WRITE_RGB;
- break;
- }
-
- START_RING(8 + ndwords);
- OUT_RING(br00);
- OUT_RING(br13);
- OUT_RING(br22);
- OUT_RING(br23);
- OUT_RING(br09);
- OUT_RING(br18);
- OUT_RING(br19);
- ix = iy = 0;
- iw = ROUND_UP_TO(w, 8) / 8;
- while (ndwords--) {
- dat = 0;
- for (j = 0; j < 2; ++j) {
- for (i = 0; i < 2; ++i) {
- if (ix != iw || i == 0)
- dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
- }
- if (ix == iw && iy != (h-1)) {
- ix = 0;
- ++iy;
- }
- }
- OUT_RING(dat);
- }
- if (pad)
- OUT_RING(MI_NOOP);
- ADVANCE_RING();
-
- return 1;
-}
-
-/* HW cursor functions. */
-void intelfbhw_cursor_init(struct intelfb_info *dinfo)
-{
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_init\n");
-#endif
-
- if (dinfo->mobile || IS_I9XX(dinfo)) {
- if (!dinfo->cursor.physical)
- return;
- tmp = INREG(CURSOR_A_CONTROL);
- tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
- CURSOR_MEM_TYPE_LOCAL |
- (1 << CURSOR_PIPE_SELECT_SHIFT));
- tmp |= CURSOR_MODE_DISABLE;
- OUTREG(CURSOR_A_CONTROL, tmp);
- OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
- } else {
- tmp = INREG(CURSOR_CONTROL);
- tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
- CURSOR_ENABLE | CURSOR_STRIDE_MASK);
- tmp |= CURSOR_FORMAT_3C;
- OUTREG(CURSOR_CONTROL, tmp);
- OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
- tmp = (64 << CURSOR_SIZE_H_SHIFT) |
- (64 << CURSOR_SIZE_V_SHIFT);
- OUTREG(CURSOR_SIZE, tmp);
- }
-}
-
-void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
-{
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_hide\n");
-#endif
-
- dinfo->cursor_on = 0;
- if (dinfo->mobile || IS_I9XX(dinfo)) {
- if (!dinfo->cursor.physical)
- return;
- tmp = INREG(CURSOR_A_CONTROL);
- tmp &= ~CURSOR_MODE_MASK;
- tmp |= CURSOR_MODE_DISABLE;
- OUTREG(CURSOR_A_CONTROL, tmp);
- /* Flush changes */
- OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
- } else {
- tmp = INREG(CURSOR_CONTROL);
- tmp &= ~CURSOR_ENABLE;
- OUTREG(CURSOR_CONTROL, tmp);
- }
-}
-
-void intelfbhw_cursor_show(struct intelfb_info *dinfo)
-{
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_show\n");
-#endif
-
- dinfo->cursor_on = 1;
-
- if (dinfo->cursor_blanked)
- return;
-
- if (dinfo->mobile || IS_I9XX(dinfo)) {
- if (!dinfo->cursor.physical)
- return;
- tmp = INREG(CURSOR_A_CONTROL);
- tmp &= ~CURSOR_MODE_MASK;
- tmp |= CURSOR_MODE_64_4C_AX;
- OUTREG(CURSOR_A_CONTROL, tmp);
- /* Flush changes */
- OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
- } else {
- tmp = INREG(CURSOR_CONTROL);
- tmp |= CURSOR_ENABLE;
- OUTREG(CURSOR_CONTROL, tmp);
- }
-}
-
-void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
-{
- u32 tmp;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
-#endif
-
- /*
- * Sets the position. The coordinates are assumed to already
- * have any offset adjusted. Assume that the cursor is never
- * completely off-screen, and that x, y are always >= 0.
- */
-
- tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
- ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
- OUTREG(CURSOR_A_POSITION, tmp);
-
- if (IS_I9XX(dinfo))
- OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
-}
-
-void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
-{
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_setcolor\n");
-#endif
-
- OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
- OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
- OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
- OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
-}
-
-void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
- u8 *data)
-{
- u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
- int i, j, w = width / 8;
- int mod = width % 8, t_mask, d_mask;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_load\n");
-#endif
-
- if (!dinfo->cursor.virtual)
- return;
-
- t_mask = 0xff >> mod;
- d_mask = ~(0xff >> mod);
- for (i = height; i--; ) {
- for (j = 0; j < w; j++) {
- writeb(0x00, addr + j);
- writeb(*(data++), addr + j+8);
- }
- if (mod) {
- writeb(t_mask, addr + j);
- writeb(*(data++) & d_mask, addr + j+8);
- }
- addr += 16;
- }
-}
-
-void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
-{
- u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
- int i, j;
-
-#if VERBOSE > 0
- DBG_MSG("intelfbhw_cursor_reset\n");
-#endif
-
- if (!dinfo->cursor.virtual)
- return;
-
- for (i = 64; i--; ) {
- for (j = 0; j < 8; j++) {
- writeb(0xff, addr + j+0);
- writeb(0x00, addr + j+8);
- }
- addr += 16;
- }
-}
-
-static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
-{
- u16 tmp;
- struct intelfb_info *dinfo = dev_id;
-
- spin_lock(&dinfo->int_lock);
-
- tmp = INREG16(IIR);
- if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
- tmp &= PIPE_A_EVENT_INTERRUPT;
- else
- tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
-
- if (tmp == 0) {
- spin_unlock(&dinfo->int_lock);
- return IRQ_RETVAL(0); /* not us */
- }
-
- /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
- OUTREG(PIPEASTAT, INREG(PIPEASTAT));
-
- OUTREG16(IIR, tmp);
- if (dinfo->vsync.pan_display) {
- dinfo->vsync.pan_display = 0;
- OUTREG(DSPABASE, dinfo->vsync.pan_offset);
- }
-
- dinfo->vsync.count++;
- wake_up_interruptible(&dinfo->vsync.wait);
-
- spin_unlock(&dinfo->int_lock);
-
- return IRQ_RETVAL(1);
-}
-
-int intelfbhw_enable_irq(struct intelfb_info *dinfo)
-{
- u16 tmp;
- if (!test_and_set_bit(0, &dinfo->irq_flags)) {
- if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
- "intelfb", dinfo)) {
- clear_bit(0, &dinfo->irq_flags);
- return -EINVAL;
- }
-
- spin_lock_irq(&dinfo->int_lock);
- OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
- OUTREG16(IMR, 0);
- } else
- spin_lock_irq(&dinfo->int_lock);
-
- if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
- tmp = PIPE_A_EVENT_INTERRUPT;
- else
- tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
- if (tmp != INREG16(IER)) {
- DBG_MSG("changing IER to 0x%X\n", tmp);
- OUTREG16(IER, tmp);
- }
-
- spin_unlock_irq(&dinfo->int_lock);
- return 0;
-}
-
-void intelfbhw_disable_irq(struct intelfb_info *dinfo)
-{
- if (test_and_clear_bit(0, &dinfo->irq_flags)) {
- if (dinfo->vsync.pan_display) {
- dinfo->vsync.pan_display = 0;
- OUTREG(DSPABASE, dinfo->vsync.pan_offset);
- }
- spin_lock_irq(&dinfo->int_lock);
- OUTREG16(HWSTAM, 0xffff);
- OUTREG16(IMR, 0xffff);
- OUTREG16(IER, 0x0);
-
- OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
- spin_unlock_irq(&dinfo->int_lock);
-
- free_irq(dinfo->pdev->irq, dinfo);
- }
-}
-
-int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
-{
- struct intelfb_vsync *vsync;
- unsigned int count;
- int ret;
-
- switch (pipe) {
- case 0:
- vsync = &dinfo->vsync;
- break;
- default:
- return -ENODEV;
- }
-
- ret = intelfbhw_enable_irq(dinfo);
- if (ret)
- return ret;
-
- count = vsync->count;
- ret = wait_event_interruptible_timeout(vsync->wait,
- count != vsync->count, HZ / 10);
- if (ret < 0)
- return ret;
- if (ret == 0) {
- DBG_MSG("wait_for_vsync timed out!\n");
- return -ETIMEDOUT;
- }
-
- return 0;
-}
diff --git a/drivers/video/fbdev/intelfb/intelfbhw.h b/drivers/video/fbdev/intelfb/intelfbhw.h
deleted file mode 100644
index 216ca20f259f..000000000000
--- a/drivers/video/fbdev/intelfb/intelfbhw.h
+++ /dev/null
@@ -1,609 +0,0 @@
-#ifndef _INTELFBHW_H
-#define _INTELFBHW_H
-
-/* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */
-
-
-/*** HW-specific data ***/
-
-/* Information about the 852GM/855GM variants */
-#define INTEL_85X_CAPID 0x44
-#define INTEL_85X_VARIANT_MASK 0x7
-#define INTEL_85X_VARIANT_SHIFT 5
-#define INTEL_VAR_855GME 0x0
-#define INTEL_VAR_855GM 0x4
-#define INTEL_VAR_852GME 0x2
-#define INTEL_VAR_852GM 0x5
-
-/* Information about DVO/LVDS Ports */
-#define DVOA_PORT 0x1
-#define DVOB_PORT 0x2
-#define DVOC_PORT 0x4
-#define LVDS_PORT 0x8
-
-/*
- * The Bridge device's PCI config space has information about the
- * fb aperture size and the amount of pre-reserved memory.
- */
-#define INTEL_GMCH_CTRL 0x52
-#define INTEL_GMCH_ENABLED 0x4
-#define INTEL_GMCH_MEM_MASK 0x1
-#define INTEL_GMCH_MEM_64M 0x1
-#define INTEL_GMCH_MEM_128M 0
-
-#define INTEL_830_GMCH_GMS_MASK (0x7 << 4)
-#define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4)
-#define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4)
-#define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4)
-#define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
-#define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
-
-#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
-#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
-#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
-#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
-#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
-#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
-#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
-
-#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
-#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
-
-/* HW registers */
-
-/* Fence registers */
-#define FENCE 0x2000
-#define FENCE_NUM 8
-
-/* Primary ring buffer */
-#define PRI_RING_TAIL 0x2030
-#define RING_TAIL_MASK 0x001ffff8
-#define RING_INUSE 0x1
-
-#define PRI_RING_HEAD 0x2034
-#define RING_HEAD_WRAP_MASK 0x7ff
-#define RING_HEAD_WRAP_SHIFT 21
-#define RING_HEAD_MASK 0x001ffffc
-
-#define PRI_RING_START 0x2038
-#define RING_START_MASK 0xfffff000
-
-#define PRI_RING_LENGTH 0x203c
-#define RING_LENGTH_MASK 0x001ff000
-#define RING_REPORT_MASK (0x3 << 1)
-#define RING_NO_REPORT (0x0 << 1)
-#define RING_REPORT_64K (0x1 << 1)
-#define RING_REPORT_4K (0x2 << 1)
-#define RING_REPORT_128K (0x3 << 1)
-#define RING_ENABLE 0x1
-
-/*
- * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
- * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
- */
-#define RING_MIN_FREE 64
-
-#define IPEHR 0x2088
-
-#define INSTDONE 0x2090
-#define PRI_RING_EMPTY 1
-
-#define HWSTAM 0x2098
-#define IER 0x20A0
-#define IIR 0x20A4
-#define IMR 0x20A8
-#define VSYNC_PIPE_A_INTERRUPT (1 << 7)
-#define PIPE_A_EVENT_INTERRUPT (1 << 6)
-#define VSYNC_PIPE_B_INTERRUPT (1 << 5)
-#define PIPE_B_EVENT_INTERRUPT (1 << 4)
-#define HOST_PORT_EVENT_INTERRUPT (1 << 3)
-#define CAPTURE_EVENT_INTERRUPT (1 << 2)
-#define USER_DEFINED_INTERRUPT (1 << 1)
-#define BREAKPOINT_INTERRUPT 1
-
-#define INSTPM 0x20c0
-#define SYNC_FLUSH_ENABLE (1 << 5)
-
-#define INSTPS 0x20c4
-
-#define MEM_MODE 0x20cc
-
-#define MASK_SHIFT 16
-
-#define FW_BLC_0 0x20d8
-#define FW_DISPA_WM_SHIFT 0
-#define FW_DISPA_WM_MASK 0x3f
-#define FW_DISPA_BL_SHIFT 8
-#define FW_DISPA_BL_MASK 0xf
-#define FW_DISPB_WM_SHIFT 16
-#define FW_DISPB_WM_MASK 0x1f
-#define FW_DISPB_BL_SHIFT 24
-#define FW_DISPB_BL_MASK 0x7
-
-#define FW_BLC_1 0x20dc
-#define FW_DISPC_WM_SHIFT 0
-#define FW_DISPC_WM_MASK 0x1f
-#define FW_DISPC_BL_SHIFT 8
-#define FW_DISPC_BL_MASK 0x7
-
-#define GPIOA 0x5010
-#define GPIOB 0x5014
-#define GPIOC 0x5018 /* this may be external DDC on i830 */
-#define GPIOD 0x501C /* this is DVO DDC */
-#define GPIOE 0x5020 /* this is DVO i2C */
-#define GPIOF 0x5024
-
-/* PLL registers */
-#define VGA0_DIVISOR 0x06000
-#define VGA1_DIVISOR 0x06004
-#define VGAPD 0x06010
-#define VGAPD_0_P1_SHIFT 0
-#define VGAPD_0_P1_FORCE_DIV2 (1 << 5)
-#define VGAPD_0_P2_SHIFT 7
-#define VGAPD_1_P1_SHIFT 8
-#define VGAPD_1_P1_FORCE_DIV2 (1 << 13)
-#define VGAPD_1_P2_SHIFT 15
-
-#define DPLL_A 0x06014
-#define DPLL_B 0x06018
-#define DPLL_VCO_ENABLE (1 << 31)
-#define DPLL_2X_CLOCK_ENABLE (1 << 30)
-#define DPLL_SYNCLOCK_ENABLE (1 << 29)
-#define DPLL_VGA_MODE_DISABLE (1 << 28)
-#define DPLL_P2_MASK 1
-#define DPLL_P2_SHIFT 23
-#define DPLL_I9XX_P2_SHIFT 24
-#define DPLL_P1_FORCE_DIV2 (1 << 21)
-#define DPLL_P1_MASK 0x1f
-#define DPLL_P1_SHIFT 16
-#define DPLL_REFERENCE_SELECT_MASK (0x3 << 13)
-#define DPLL_REFERENCE_DEFAULT (0x0 << 13)
-#define DPLL_REFERENCE_TVCLK (0x2 << 13)
-#define DPLL_RATE_SELECT_MASK (1 << 8)
-#define DPLL_RATE_SELECT_FP0 (0 << 8)
-#define DPLL_RATE_SELECT_FP1 (1 << 8)
-
-#define FPA0 0x06040
-#define FPA1 0x06044
-#define FPB0 0x06048
-#define FPB1 0x0604c
-#define FP_DIVISOR_MASK 0x3f
-#define FP_N_DIVISOR_SHIFT 16
-#define FP_M1_DIVISOR_SHIFT 8
-#define FP_M2_DIVISOR_SHIFT 0
-
-/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
-/* Clock values are in units of kHz */
-#define PLL_REFCLK 48000
-#define MIN_CLOCK 25000
-#define MAX_CLOCK 350000
-
-/* Two pipes */
-#define PIPE_A 0
-#define PIPE_B 1
-#define PIPE_MASK 1
-
-/* palette registers */
-#define PALETTE_A 0x0a000
-#define PALETTE_B 0x0a800
-#ifndef PALETTE_8_ENTRIES
-#define PALETTE_8_ENTRIES 256
-#endif
-#define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4)
-#define PALETTE_10_ENTRIES 128
-#define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8)
-#define PALETTE_8_MASK 0xff
-#define PALETTE_8_RED_SHIFT 16
-#define PALETTE_8_GREEN_SHIFT 8
-#define PALETTE_8_BLUE_SHIFT 0
-
-/* CRTC registers */
-#define HTOTAL_A 0x60000
-#define HBLANK_A 0x60004
-#define HSYNC_A 0x60008
-#define VTOTAL_A 0x6000c
-#define VBLANK_A 0x60010
-#define VSYNC_A 0x60014
-#define SRC_SIZE_A 0x6001c
-#define BCLRPAT_A 0x60020
-
-#define HTOTAL_B 0x61000
-#define HBLANK_B 0x61004
-#define HSYNC_B 0x61008
-#define VTOTAL_B 0x6100c
-#define VBLANK_B 0x61010
-#define VSYNC_B 0x61014
-#define SRC_SIZE_B 0x6101c
-#define BCLRPAT_B 0x61020
-
-#define HTOTAL_MASK 0xfff
-#define HTOTAL_SHIFT 16
-#define HACTIVE_MASK 0x7ff
-#define HACTIVE_SHIFT 0
-#define HBLANKEND_MASK 0xfff
-#define HBLANKEND_SHIFT 16
-#define HBLANKSTART_MASK 0xfff
-#define HBLANKSTART_SHIFT 0
-#define HSYNCEND_MASK 0xfff
-#define HSYNCEND_SHIFT 16
-#define HSYNCSTART_MASK 0xfff
-#define HSYNCSTART_SHIFT 0
-#define VTOTAL_MASK 0xfff
-#define VTOTAL_SHIFT 16
-#define VACTIVE_MASK 0x7ff
-#define VACTIVE_SHIFT 0
-#define VBLANKEND_MASK 0xfff
-#define VBLANKEND_SHIFT 16
-#define VBLANKSTART_MASK 0xfff
-#define VBLANKSTART_SHIFT 0
-#define VSYNCEND_MASK 0xfff
-#define VSYNCEND_SHIFT 16
-#define VSYNCSTART_MASK 0xfff
-#define VSYNCSTART_SHIFT 0
-#define SRC_SIZE_HORIZ_MASK 0x7ff
-#define SRC_SIZE_HORIZ_SHIFT 16
-#define SRC_SIZE_VERT_MASK 0x7ff
-#define SRC_SIZE_VERT_SHIFT 0
-
-#define ADPA 0x61100
-#define ADPA_DAC_ENABLE (1 << 31)
-#define ADPA_DAC_DISABLE 0
-#define ADPA_PIPE_SELECT_SHIFT 30
-#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
-#define ADPA_SETS_HVPOLARITY 0
-#define ADPA_DPMS_CONTROL_MASK (0x3 << 10)
-#define ADPA_DPMS_D0 (0x0 << 10)
-#define ADPA_DPMS_D2 (0x1 << 10)
-#define ADPA_DPMS_D1 (0x2 << 10)
-#define ADPA_DPMS_D3 (0x3 << 10)
-#define ADPA_VSYNC_ACTIVE_SHIFT 4
-#define ADPA_HSYNC_ACTIVE_SHIFT 3
-#define ADPA_SYNC_ACTIVE_MASK 1
-#define ADPA_SYNC_ACTIVE_HIGH 1
-#define ADPA_SYNC_ACTIVE_LOW 0
-
-#define DVOA 0x61120
-#define DVOB 0x61140
-#define DVOC 0x61160
-#define LVDS 0x61180
-#define PORT_ENABLE (1 << 31)
-#define PORT_PIPE_SELECT_SHIFT 30
-#define PORT_TV_FLAGS_MASK 0xFF
-#define PORT_TV_FLAGS 0xC4 /* ripped from my BIOS
- to understand and correct */
-
-#define DVOA_SRCDIM 0x61124
-#define DVOB_SRCDIM 0x61144
-#define DVOC_SRCDIM 0x61164
-
-#define PIPEA_DSL 0x70000
-#define PIPEB_DSL 0x71000
-#define PIPEACONF 0x70008
-#define PIPEBCONF 0x71008
-#define PIPEASTAT 0x70024 /* bits 0-15 are "write 1 to clear" */
-#define PIPEBSTAT 0x71024
-
-#define PIPECONF_ENABLE (1 << 31)
-#define PIPECONF_DISABLE 0
-#define PIPECONF_DOUBLE_WIDE (1 << 30)
-#define PIPECONF_SINGLE_WIDE 0
-#define PIPECONF_LOCKED (1 << 25)
-#define PIPECONF_UNLOCKED 0
-#define PIPECONF_GAMMA (1 << 24)
-#define PIPECONF_PALETTE 0
-#define PIPECONF_PROGRESSIVE (0 << 21)
-#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
-#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
-#define PIPECONF_INTERLACE_MASK (7 << 21)
-
-/* enable bits, write 1 to enable */
-#define PIPESTAT_FIFO_UNDERRUN (1 << 31)
-#define PIPESTAT_CRC_ERROR_EN (1 << 29)
-#define PIPESTAT_CRC_DONE_EN (1 << 28)
-#define PIPESTAT_HOTPLUG_EN (1 << 26)
-#define PIPESTAT_VERTICAL_SYNC_EN (1 << 25)
-#define PIPESTAT_DISPLINE_COMP_EN (1 << 24)
-#define PIPESTAT_FLD_EVT_ODD_EN (1 << 21)
-#define PIPESTAT_FLD_EVT_EVEN_EN (1 << 20)
-#define PIPESTAT_TV_HOTPLUG_EN (1 << 18)
-#define PIPESTAT_VBLANK_EN (1 << 17)
-#define PIPESTAT_OVL_UPDATE_EN (1 << 16)
-/* status bits, write 1 to clear */
-#define PIPESTAT_HOTPLUG_STATE (1 << 15)
-#define PIPESTAT_CRC_ERROR (1 << 13)
-#define PIPESTAT_CRC_DONE (1 << 12)
-#define PIPESTAT_HOTPLUG (1 << 10)
-#define PIPESTAT_VSYNC (1 << 9)
-#define PIPESTAT_DISPLINE_COMP (1 << 8)
-#define PIPESTAT_FLD_EVT_ODD (1 << 5)
-#define PIPESTAT_FLD_EVT_EVEN (1 << 4)
-#define PIPESTAT_TV_HOTPLUG (1 << 2)
-#define PIPESTAT_VBLANK (1 << 1)
-#define PIPESTAT_OVL_UPDATE (1 << 0)
-
-#define DISPARB 0x70030
-#define DISPARB_AEND_MASK 0x1ff
-#define DISPARB_AEND_SHIFT 0
-#define DISPARB_BEND_MASK 0x3ff
-#define DISPARB_BEND_SHIFT 9
-
-/* Desktop HW cursor */
-#define CURSOR_CONTROL 0x70080
-#define CURSOR_ENABLE (1 << 31)
-#define CURSOR_GAMMA_ENABLE (1 << 30)
-#define CURSOR_STRIDE_MASK (0x3 << 28)
-#define CURSOR_STRIDE_256 (0x0 << 28)
-#define CURSOR_STRIDE_512 (0x1 << 28)
-#define CURSOR_STRIDE_1K (0x2 << 28)
-#define CURSOR_STRIDE_2K (0x3 << 28)
-#define CURSOR_FORMAT_MASK (0x7 << 24)
-#define CURSOR_FORMAT_2C (0x0 << 24)
-#define CURSOR_FORMAT_3C (0x1 << 24)
-#define CURSOR_FORMAT_4C (0x2 << 24)
-#define CURSOR_FORMAT_ARGB (0x4 << 24)
-#define CURSOR_FORMAT_XRGB (0x5 << 24)
-
-/* Mobile HW cursor (and i810) */
-#define CURSOR_A_CONTROL CURSOR_CONTROL
-#define CURSOR_B_CONTROL 0x700c0
-#define CURSOR_MODE_MASK 0x27
-#define CURSOR_MODE_DISABLE 0
-#define CURSOR_MODE_64_3C 0x04
-#define CURSOR_MODE_64_4C_AX 0x05
-#define CURSOR_MODE_64_4C 0x06
-#define CURSOR_MODE_64_32B_AX 0x07
-#define CURSOR_MODE_64_ARGB_AX 0x27
-#define CURSOR_PIPE_SELECT_SHIFT 28
-#define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26)
-#define CURSOR_MEM_TYPE_LOCAL (1 << 25)
-
-/* All platforms (desktop has no pipe B) */
-#define CURSOR_A_BASEADDR 0x70084
-#define CURSOR_B_BASEADDR 0x700c4
-#define CURSOR_BASE_MASK 0xffffff00
-
-#define CURSOR_A_POSITION 0x70088
-#define CURSOR_B_POSITION 0x700c8
-#define CURSOR_POS_SIGN (1 << 15)
-#define CURSOR_POS_MASK 0x7ff
-#define CURSOR_X_SHIFT 0
-#define CURSOR_Y_SHIFT 16
-
-#define CURSOR_A_PALETTE0 0x70090
-#define CURSOR_A_PALETTE1 0x70094
-#define CURSOR_A_PALETTE2 0x70098
-#define CURSOR_A_PALETTE3 0x7009c
-#define CURSOR_B_PALETTE0 0x700d0
-#define CURSOR_B_PALETTE1 0x700d4
-#define CURSOR_B_PALETTE2 0x700d8
-#define CURSOR_B_PALETTE3 0x700dc
-#define CURSOR_COLOR_MASK 0xff
-#define CURSOR_RED_SHIFT 16
-#define CURSOR_GREEN_SHIFT 8
-#define CURSOR_BLUE_SHIFT 0
-#define CURSOR_PALETTE_MASK 0xffffff
-
-/* Desktop only */
-#define CURSOR_SIZE 0x700a0
-#define CURSOR_SIZE_MASK 0x3ff
-#define CURSOR_SIZE_H_SHIFT 0
-#define CURSOR_SIZE_V_SHIFT 12
-
-#define DSPACNTR 0x70180
-#define DSPBCNTR 0x71180
-#define DISPPLANE_PLANE_ENABLE (1 << 31)
-#define DISPPLANE_PLANE_DISABLE 0
-#define DISPPLANE_GAMMA_ENABLE (1<<30)
-#define DISPPLANE_GAMMA_DISABLE 0
-#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
-#define DISPPLANE_8BPP (0x2<<26)
-#define DISPPLANE_15_16BPP (0x4<<26)
-#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
-#define DISPPLANE_32BPP (0x7<<26)
-#define DISPPLANE_STEREO_ENABLE (1<<25)
-#define DISPPLANE_STEREO_DISABLE 0
-#define DISPPLANE_SEL_PIPE_SHIFT 24
-#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
-#define DISPPLANE_SRC_KEY_DISABLE 0
-#define DISPPLANE_LINE_DOUBLE (1<<20)
-#define DISPPLANE_NO_LINE_DOUBLE 0
-#define DISPPLANE_STEREO_POLARITY_FIRST 0
-#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
-/* plane B only */
-#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
-#define DISPPLANE_ALPHA_TRANS_DISABLE 0
-#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
-#define DISPPLANE_SPRITE_ABOVE_OVERLAY 1
-
-#define DSPABASE 0x70184
-#define DSPASTRIDE 0x70188
-
-#define DSPBBASE 0x71184
-#define DSPBSTRIDE 0x71188
-
-#define VGACNTRL 0x71400
-#define VGA_DISABLE (1 << 31)
-#define VGA_ENABLE 0
-#define VGA_PIPE_SELECT_SHIFT 29
-#define VGA_PALETTE_READ_SELECT 23
-#define VGA_PALETTE_A_WRITE_DISABLE (1 << 22)
-#define VGA_PALETTE_B_WRITE_DISABLE (1 << 21)
-#define VGA_LEGACY_PALETTE (1 << 20)
-#define VGA_6BIT_DAC 0
-#define VGA_8BIT_DAC (1 << 20)
-
-#define ADD_ID 0x71408
-#define ADD_ID_MASK 0xff
-
-/* BIOS scratch area registers (830M and 845G). */
-#define SWF0 0x71410
-#define SWF1 0x71414
-#define SWF2 0x71418
-#define SWF3 0x7141c
-#define SWF4 0x71420
-#define SWF5 0x71424
-#define SWF6 0x71428
-
-/* BIOS scratch area registers (852GM, 855GM, 865G). */
-#define SWF00 0x70410
-#define SWF01 0x70414
-#define SWF02 0x70418
-#define SWF03 0x7041c
-#define SWF04 0x70420
-#define SWF05 0x70424
-#define SWF06 0x70428
-
-#define SWF10 SWF0
-#define SWF11 SWF1
-#define SWF12 SWF2
-#define SWF13 SWF3
-#define SWF14 SWF4
-#define SWF15 SWF5
-#define SWF16 SWF6
-
-#define SWF30 0x72414
-#define SWF31 0x72418
-#define SWF32 0x7241c
-
-/* Memory Commands */
-#define MI_NOOP (0x00 << 23)
-#define MI_NOOP_WRITE_ID (1 << 22)
-#define MI_NOOP_ID_MASK ((1 << 22) - 1)
-
-#define MI_FLUSH (0x04 << 23)
-#define MI_WRITE_DIRTY_STATE (1 << 4)
-#define MI_END_SCENE (1 << 3)
-#define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
-#define MI_INVALIDATE_MAP_CACHE (1 << 0)
-
-#define MI_STORE_DWORD_IMM ((0x20 << 23) | 1)
-
-/* 2D Commands */
-#define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3)
-#define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4)
-#define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1)
-#define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6)
-#define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4)
-#define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7)
-#define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6)
-#define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5)
-#define TXT_IMM_BLT_CMD ((2 << 29) | (0x30 << 22) | 2)
-#define SETUP_BLT_CMD ((2 << 29) | (0x00 << 22) | 6)
-
-#define DW_LENGTH_MASK 0xff
-
-#define WRITE_ALPHA (1 << 21)
-#define WRITE_RGB (1 << 20)
-#define VERT_SEED (3 << 8)
-#define HORIZ_SEED (3 << 12)
-
-#define COLOR_DEPTH_8 (0 << 24)
-#define COLOR_DEPTH_16 (1 << 24)
-#define COLOR_DEPTH_32 (3 << 24)
-
-#define SRC_ROP_GXCOPY 0xcc
-#define SRC_ROP_GXXOR 0x66
-
-#define PAT_ROP_GXCOPY 0xf0
-#define PAT_ROP_GXXOR 0x5a
-
-#define PITCH_SHIFT 0
-#define ROP_SHIFT 16
-#define WIDTH_SHIFT 0
-#define HEIGHT_SHIFT 16
-
-/* in bytes */
-#define MAX_MONO_IMM_SIZE 128
-
-
-/*** Macros ***/
-
-/* I/O macros */
-#define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
-#define INREG16(addr) readw((u16 __iomem *)(dinfo->mmio_base + (addr)))
-#define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
-#define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
- (addr)))
-#define OUTREG16(addr, val) writew((val),(u16 __iomem *)(dinfo->mmio_base + \
- (addr)))
-#define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \
- (addr)))
-
-/* Ring buffer macros */
-#define OUT_RING(n) do { \
- writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
- dinfo->ring_tail += 4; \
- dinfo->ring_tail &= dinfo->ring_tail_mask; \
-} while (0)
-
-#define START_RING(n) do { \
- if (dinfo->ring_space < (n) * 4) \
- wait_ring(dinfo,(n) * 4); \
- dinfo->ring_space -= (n) * 4; \
-} while (0)
-
-#define ADVANCE_RING() do { \
- OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
-} while (0)
-
-#define DO_RING_IDLE() do { \
- u32 head, tail; \
- do { \
- head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
- tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
- udelay(10); \
- } while (head != tail); \
-} while (0)
-
-
-/* function protoypes */
-extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
-extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
- int *stolen_size);
-extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
-extern const char *intelfbhw_dvo_to_string(int dvo);
-extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
- struct fb_var_screeninfo *var);
-extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info);
-extern void intelfbhw_do_blank(int blank, struct fb_info *info);
-extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
- unsigned red, unsigned green, unsigned blue,
- unsigned transp);
-extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw, int flag);
-extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw);
-extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
- struct intelfb_hwstate *hw,
- struct fb_var_screeninfo *var);
-extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
- const struct intelfb_hwstate *hw, int blank);
-extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
-extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
-extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
-extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
- u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
- u32 rop);
-extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
- u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
- u32 bpp);
-extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
- u32 w, u32 h, const u8* cdat, u32 x, u32 y,
- u32 pitch, u32 bpp);
-extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
-extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
-extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
-extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
-extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
- u32 fg);
-extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
- int height, u8 *data);
-extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
-extern int intelfbhw_enable_irq(struct intelfb_info *dinfo);
-extern void intelfbhw_disable_irq(struct intelfb_info *dinfo);
-extern int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe);
-extern int intelfbhw_active_pipe(const struct intelfb_hwstate *hw);
-
-#endif /* _INTELFBHW_H */
diff --git a/drivers/video/fbdev/matrox/i2c-matroxfb.c b/drivers/video/fbdev/matrox/i2c-matroxfb.c
index e2e4705e3fe0..bb048e14b2cf 100644
--- a/drivers/video/fbdev/matrox/i2c-matroxfb.c
+++ b/drivers/video/fbdev/matrox/i2c-matroxfb.c
@@ -100,8 +100,7 @@ static const struct i2c_algo_bit_data matrox_i2c_algo_template =
};
static int i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo,
- unsigned int data, unsigned int clock, const char *name,
- int class)
+ unsigned int data, unsigned int clock, const char *name)
{
int err;
@@ -112,7 +111,6 @@ static int i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo,
snprintf(b->adapter.name, sizeof(b->adapter.name), name,
minfo->fbcon.node);
i2c_set_adapdata(&b->adapter, b);
- b->adapter.class = class;
b->adapter.algo_data = &b->bac;
b->adapter.dev.parent = &minfo->pcidev->dev;
b->bac = matrox_i2c_algo_template;
@@ -160,27 +158,24 @@ static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
case MGA_2164:
err = i2c_bus_reg(&m2info->ddc1, minfo,
DDC1B_DATA, DDC1B_CLK,
- "DDC:fb%u #0", I2C_CLASS_DDC);
+ "DDC:fb%u #0");
break;
default:
err = i2c_bus_reg(&m2info->ddc1, minfo,
DDC1_DATA, DDC1_CLK,
- "DDC:fb%u #0", I2C_CLASS_DDC);
+ "DDC:fb%u #0");
break;
}
if (err)
goto fail_ddc1;
if (minfo->devflags.dualhead) {
- err = i2c_bus_reg(&m2info->ddc2, minfo,
- DDC2_DATA, DDC2_CLK,
- "DDC:fb%u #1", I2C_CLASS_DDC);
+ err = i2c_bus_reg(&m2info->ddc2, minfo, DDC2_DATA, DDC2_CLK, "DDC:fb%u #1");
if (err == -ENODEV) {
printk(KERN_INFO "i2c-matroxfb: VGA->TV plug detected, DDC unavailable.\n");
} else if (err)
printk(KERN_INFO "i2c-matroxfb: Could not register secondary output i2c bus. Continuing anyway.\n");
/* Register maven bus even on G450/G550 */
- err = i2c_bus_reg(&m2info->maven, minfo,
- MAT_DATA, MAT_CLK, "MAVEN:fb%u", 0);
+ err = i2c_bus_reg(&m2info->maven, minfo, MAT_DATA, MAT_CLK, "MAVEN:fb%u");
if (err)
printk(KERN_INFO "i2c-matroxfb: Could not register Maven i2c bus. Continuing anyway.\n");
else {
diff --git a/drivers/video/fbdev/mmp/hw/mmp_spi.c b/drivers/video/fbdev/mmp/hw/mmp_spi.c
index 16401eb95c6c..0f8f0312a7c4 100644
--- a/drivers/video/fbdev/mmp/hw/mmp_spi.c
+++ b/drivers/video/fbdev/mmp/hw/mmp_spi.c
@@ -91,7 +91,7 @@ static int lcd_spi_setup(struct spi_device *spi)
writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
/*
- * After set mode it need a time to pull up the spi singals,
+ * After set mode it needs some time to pull up the spi signals,
* or it would cause the wrong waveform when send spi command,
* especially on pxa910h
*/
diff --git a/drivers/video/fbdev/s3fb.c b/drivers/video/fbdev/s3fb.c
index 589b349cb63e..07722a5ea8ef 100644
--- a/drivers/video/fbdev/s3fb.c
+++ b/drivers/video/fbdev/s3fb.c
@@ -252,7 +252,6 @@ static int s3fb_setup_ddc_bus(struct fb_info *info)
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
- par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
par->ddc_algo.setsda = s3fb_ddc_setsda;
diff --git a/drivers/video/fbdev/sis/sis_main.c b/drivers/video/fbdev/sis/sis_main.c
index 6ad47b6b6004..803ccb6aa479 100644
--- a/drivers/video/fbdev/sis/sis_main.c
+++ b/drivers/video/fbdev/sis/sis_main.c
@@ -27,7 +27,6 @@
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
-#include <linux/screen_info.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/selection.h>
@@ -257,36 +256,6 @@ static void sisfb_search_mode(char *name, bool quiet)
printk(KERN_ERR "sisfb: Invalid mode '%s'\n", nameptr);
}
-#ifndef MODULE
-static void sisfb_get_vga_mode_from_kernel(void)
-{
-#ifdef CONFIG_X86
- char mymode[32];
- int mydepth = screen_info.lfb_depth;
-
- if(screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB) return;
-
- if( (screen_info.lfb_width >= 320) && (screen_info.lfb_width <= 2048) &&
- (screen_info.lfb_height >= 200) && (screen_info.lfb_height <= 1536) &&
- (mydepth >= 8) && (mydepth <= 32) ) {
-
- if(mydepth == 24) mydepth = 32;
-
- sprintf(mymode, "%ux%ux%u", screen_info.lfb_width,
- screen_info.lfb_height,
- mydepth);
-
- printk(KERN_DEBUG
- "sisfb: Using vga mode %s pre-set by kernel as default\n",
- mymode);
-
- sisfb_search_mode(mymode, true);
- }
-#endif
- return;
-}
-#endif
-
static void __init
sisfb_search_crt2type(const char *name)
{
@@ -5901,12 +5870,6 @@ static int sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
ivideo->subsysvendor = pdev->subsystem_vendor;
ivideo->subsysdevice = pdev->subsystem_device;
-#ifndef MODULE
- if(sisfb_mode_idx == -1) {
- sisfb_get_vga_mode_from_kernel();
- }
-#endif
-
ivideo->chip = chipinfo->chip;
ivideo->chip_real_id = chipinfo->chip;
ivideo->sisvga_engine = chipinfo->vgaengine;
diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c
index 5ae48e36fccb..1a4f90ea7d5a 100644
--- a/drivers/video/fbdev/ssd1307fb.c
+++ b/drivers/video/fbdev/ssd1307fb.c
@@ -347,7 +347,7 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
pwm_init_state(par->pwm, &pwmstate);
pwm_set_relative_duty_cycle(&pwmstate, 50, 100);
- pwm_apply_state(par->pwm, &pwmstate);
+ pwm_apply_might_sleep(par->pwm, &pwmstate);
/* Enable the PWM */
pwm_enable(par->pwm);
diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c
index 548d992f8cb1..2de0e675fd15 100644
--- a/drivers/video/fbdev/stifb.c
+++ b/drivers/video/fbdev/stifb.c
@@ -103,7 +103,7 @@ typedef struct {
} ngle_rom_t;
struct stifb_info {
- struct fb_info info;
+ struct fb_info *info;
unsigned int id;
ngle_rom_t ngle_rom;
struct sti_struct *sti;
@@ -153,15 +153,15 @@ static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
#define REG_44 0x210030
#define REG_45 0x210034
-#define READ_BYTE(fb,reg) gsc_readb((fb)->info.fix.mmio_start + (reg))
-#define READ_WORD(fb,reg) gsc_readl((fb)->info.fix.mmio_start + (reg))
+#define READ_BYTE(fb, reg) gsc_readb((fb)->info->fix.mmio_start + (reg))
+#define READ_WORD(fb, reg) gsc_readl((fb)->info->fix.mmio_start + (reg))
#ifndef DEBUG_STIFB_REGS
# define DEBUG_OFF()
# define DEBUG_ON()
-# define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg))
-# define WRITE_WORD(value,fb,reg) gsc_writel((value),(fb)->info.fix.mmio_start + (reg))
+# define WRITE_BYTE(value, fb, reg) gsc_writeb((value), (fb)->info->fix.mmio_start + (reg))
+# define WRITE_WORD(value, fb, reg) gsc_writel((value), (fb)->info->fix.mmio_start + (reg))
#else
static int debug_on = 1;
# define DEBUG_OFF() debug_on=0
@@ -169,11 +169,11 @@ static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
# define WRITE_BYTE(value,fb,reg) do { if (debug_on) \
printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
__func__, reg, value, READ_BYTE(fb,reg)); \
- gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
+ gsc_writeb((value), (fb)->info->fix.mmio_start + (reg)); } while (0)
# define WRITE_WORD(value,fb,reg) do { if (debug_on) \
printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
__func__, reg, value, READ_WORD(fb,reg)); \
- gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
+ gsc_writel((value), (fb)->info->fix.mmio_start + (reg)); } while (0)
#endif /* DEBUG_STIFB_REGS */
@@ -210,13 +210,13 @@ SETUP_FB(struct stifb_info *fb)
reg10_value = 0x13601000;
break;
case S9000_ID_A1439A:
- if (fb->info.var.bits_per_pixel == 32)
+ if (fb->info->var.bits_per_pixel == 32)
reg10_value = 0xBBA0A000;
else
reg10_value = 0x13601000;
break;
case S9000_ID_HCRX:
- if (fb->info.var.bits_per_pixel == 32)
+ if (fb->info->var.bits_per_pixel == 32)
reg10_value = 0xBBA0A000;
else
reg10_value = 0x13602000;
@@ -254,7 +254,7 @@ static void
FINISH_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
{
WRITE_WORD(0x400, fb, REG_2);
- if (fb->info.var.bits_per_pixel == 32) {
+ if (fb->info->var.bits_per_pixel == 32) {
WRITE_WORD(0x83000100, fb, REG_1);
} else {
if (fb->id == S9000_ID_ARTIST || fb->id == CRT_ID_VISUALIZE_EG)
@@ -503,7 +503,7 @@ static void
ngleSetupAttrPlanes(struct stifb_info *fb, int BufferNumber)
{
SETUP_ATTR_ACCESS(fb, BufferNumber);
- SET_ATTR_SIZE(fb, fb->info.var.xres, fb->info.var.yres);
+ SET_ATTR_SIZE(fb, fb->info->var.xres, fb->info->var.yres);
FINISH_ATTR_ACCESS(fb);
SETUP_FB(fb);
}
@@ -526,9 +526,9 @@ rattlerSetupPlanes(struct stifb_info *fb)
SETUP_FB(fb);
fb->id = saved_id;
- for (y = 0; y < fb->info.var.yres; ++y)
- fb_memset_io(fb->info.screen_base + y * fb->info.fix.line_length,
- 0xff, fb->info.var.xres * fb->info.var.bits_per_pixel/8);
+ for (y = 0; y < fb->info->var.yres; ++y)
+ fb_memset_io(fb->info->screen_base + y * fb->info->fix.line_length,
+ 0xff, fb->info->var.xres * fb->info->var.bits_per_pixel/8);
CRX24_SET_OVLY_MASK(fb);
SETUP_FB(fb);
@@ -607,7 +607,7 @@ setHyperLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
lutBltCtl.fields.lutType = HYPER_CMAP_TYPE;
/* Expect lutIndex to be 0 or 1 for image cmaps, 2 or 3 for overlay cmaps */
- if (fb->info.var.bits_per_pixel == 8)
+ if (fb->info->var.bits_per_pixel == 8)
lutBltCtl.fields.lutOffset = 2 * 256;
else
lutBltCtl.fields.lutOffset = 0 * 256;
@@ -688,7 +688,7 @@ ngleResetAttrPlanes(struct stifb_info *fb, unsigned int ctlPlaneReg)
DataDynamic, MaskOtc,
BGx(0), FGx(0)));
packed_dst = 0;
- packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
+ packed_len = (fb->info->var.xres << 16) | fb->info->var.yres;
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
NGLE_SET_DSTXY(fb, packed_dst);
SET_LENXY_START_RECFILL(fb, packed_len);
@@ -738,7 +738,7 @@ ngleClearOverlayPlanes(struct stifb_info *fb, int mask, int data)
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, mask);
packed_dst = 0;
- packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
+ packed_len = (fb->info->var.xres << 16) | fb->info->var.yres;
NGLE_SET_DSTXY(fb, packed_dst);
/* Write zeroes to overlay planes */
@@ -760,7 +760,7 @@ hyperResetPlanes(struct stifb_info *fb, int enable)
NGLE_LOCK(fb);
if (IS_24_DEVICE(fb))
- if (fb->info.var.bits_per_pixel == 32)
+ if (fb->info->var.bits_per_pixel == 32)
controlPlaneReg = 0x04000F00;
else
controlPlaneReg = 0x00000F00; /* 0x00000800 should be enough, but lets clear all 4 bits */
@@ -890,7 +890,7 @@ SETUP_HCRX(struct stifb_info *fb)
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
if (IS_24_DEVICE(fb)) {
- hyperbowl = (fb->info.var.bits_per_pixel == 32) ?
+ hyperbowl = (fb->info->var.bits_per_pixel == 32) ?
HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE :
HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE;
@@ -924,21 +924,21 @@ SETUP_HCRX(struct stifb_info *fb)
static int
stifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
- struct stifb_info *fb = container_of(info, struct stifb_info, info);
+ struct stifb_info *fb = info->par;
- if (var->xres != fb->info.var.xres ||
- var->yres != fb->info.var.yres ||
- var->bits_per_pixel != fb->info.var.bits_per_pixel)
+ if (var->xres != fb->info->var.xres ||
+ var->yres != fb->info->var.yres ||
+ var->bits_per_pixel != fb->info->var.bits_per_pixel)
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->xoffset = 0;
var->yoffset = 0;
- var->grayscale = fb->info.var.grayscale;
- var->red.length = fb->info.var.red.length;
- var->green.length = fb->info.var.green.length;
- var->blue.length = fb->info.var.blue.length;
+ var->grayscale = fb->info->var.grayscale;
+ var->red.length = fb->info->var.red.length;
+ var->green.length = fb->info->var.green.length;
+ var->blue.length = fb->info->var.blue.length;
return 0;
}
@@ -947,7 +947,7 @@ static int
stifb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp, struct fb_info *info)
{
- struct stifb_info *fb = container_of(info, struct stifb_info, info);
+ struct stifb_info *fb = info->par;
u32 color;
if (regno >= NR_PALETTE)
@@ -961,7 +961,7 @@ stifb_setcolreg(u_int regno, u_int red, u_int green,
START_IMAGE_COLORMAP_ACCESS(fb);
- if (unlikely(fb->info.var.grayscale)) {
+ if (unlikely(fb->info->var.grayscale)) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
color = ((red * 77) +
(green * 151) +
@@ -972,10 +972,10 @@ stifb_setcolreg(u_int regno, u_int red, u_int green,
(blue));
}
- if (fb->info.fix.visual == FB_VISUAL_DIRECTCOLOR) {
- struct fb_var_screeninfo *var = &fb->info.var;
+ if (fb->info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
+ struct fb_var_screeninfo *var = &fb->info->var;
if (regno < 16)
- ((u32 *)fb->info.pseudo_palette)[regno] =
+ ((u32 *)fb->info->pseudo_palette)[regno] =
regno << var->red.offset |
regno << var->green.offset |
regno << var->blue.offset;
@@ -1007,7 +1007,7 @@ stifb_setcolreg(u_int regno, u_int red, u_int green,
static int
stifb_blank(int blank_mode, struct fb_info *info)
{
- struct stifb_info *fb = container_of(info, struct stifb_info, info);
+ struct stifb_info *fb = info->par;
int enable = (blank_mode == 0) ? ENABLE : DISABLE;
switch (fb->id) {
@@ -1036,12 +1036,12 @@ stifb_blank(int blank_mode, struct fb_info *info)
static void
stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
- struct stifb_info *fb = container_of(info, struct stifb_info, info);
+ struct stifb_info *fb = info->par;
SETUP_COPYAREA(fb);
SETUP_HW(fb);
- if (fb->info.var.bits_per_pixel == 32) {
+ if (fb->info->var.bits_per_pixel == 32) {
WRITE_WORD(0xBBA0A000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
@@ -1075,15 +1075,15 @@ stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
static void
stifb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
- struct stifb_info *fb = container_of(info, struct stifb_info, info);
+ struct stifb_info *fb = info->par;
if (rect->rop != ROP_COPY ||
- (fb->id == S9000_ID_HCRX && fb->info.var.bits_per_pixel == 32))
+ (fb->id == S9000_ID_HCRX && fb->info->var.bits_per_pixel == 32))
return cfb_fillrect(info, rect);
SETUP_HW(fb);
- if (fb->info.var.bits_per_pixel == 32) {
+ if (fb->info->var.bits_per_pixel == 32) {
WRITE_WORD(0xBBA0A000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
@@ -1141,7 +1141,7 @@ stifb_init_display(struct stifb_info *fb)
switch (id) {
case S9000_ID_A1659A:
case S9000_ID_A1439A:
- if (fb->info.var.bits_per_pixel == 32)
+ if (fb->info->var.bits_per_pixel == 32)
ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
else {
ngleSetupAttrPlanes(fb, BUFF1_CMAP0);
@@ -1151,7 +1151,7 @@ stifb_init_display(struct stifb_info *fb)
break;
case S9000_ID_ARTIST:
case CRT_ID_VISUALIZE_EG:
- if (fb->info.var.bits_per_pixel == 32)
+ if (fb->info->var.bits_per_pixel == 32)
ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
else {
ngleSetupAttrPlanes(fb, ARTIST_CMAP0);
@@ -1193,11 +1193,11 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
char *dev_name;
int bpp, xres, yres;
- fb = kzalloc(sizeof(*fb), GFP_ATOMIC);
- if (!fb)
+ info = framebuffer_alloc(sizeof(*fb), sti->dev);
+ if (!info)
return -ENOMEM;
-
- info = &fb->info;
+ fb = info->par;
+ fb->info = info;
/* set struct to a known state */
fix = &info->fix;
@@ -1389,11 +1389,10 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
}
/* save for primary gfx device detection & unregister_framebuffer() */
- sti->info = info;
- if (register_framebuffer(&fb->info) < 0)
+ if (register_framebuffer(fb->info) < 0)
goto out_err4;
- fb_info(&fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n",
+ fb_info(fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n",
fix->id,
var->xres,
var->yres,
@@ -1402,6 +1401,8 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
fb->id,
fix->mmio_start);
+ dev_set_drvdata(sti->dev, info);
+
return 0;
@@ -1414,8 +1415,7 @@ out_err2:
out_err1:
iounmap(info->screen_base);
out_err0:
- kfree(fb);
- sti->info = NULL;
+ framebuffer_release(info);
return -ENXIO;
}
@@ -1480,17 +1480,20 @@ stifb_cleanup(void)
sti = sti_get_rom(i);
if (!sti)
break;
- if (sti->info) {
- struct fb_info *info = sti->info;
- unregister_framebuffer(sti->info);
+ if (sti->dev) {
+ struct fb_info *info = dev_get_drvdata(sti->dev);
+
+ if (!info)
+ continue;
+ unregister_framebuffer(info);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
release_mem_region(info->fix.smem_start, info->fix.smem_len);
if (info->screen_base)
iounmap(info->screen_base);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
+ dev_set_drvdata(sti->dev, NULL);
}
- sti->info = NULL;
}
}
diff --git a/drivers/video/fbdev/tdfxfb.c b/drivers/video/fbdev/tdfxfb.c
index 22aa953138b0..51ebe78359ec 100644
--- a/drivers/video/fbdev/tdfxfb.c
+++ b/drivers/video/fbdev/tdfxfb.c
@@ -1267,7 +1267,6 @@ static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name,
strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
chan->adapter.owner = THIS_MODULE;
- chan->adapter.class = I2C_CLASS_DDC;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = dev;
chan->algo.setsda = tdfxfb_ddc_setsda;
diff --git a/drivers/video/fbdev/tridentfb.c b/drivers/video/fbdev/tridentfb.c
index 816d40b6f689..516cf2a18757 100644
--- a/drivers/video/fbdev/tridentfb.c
+++ b/drivers/video/fbdev/tridentfb.c
@@ -274,7 +274,6 @@ static int tridentfb_setup_ddc_bus(struct fb_info *info)
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
- par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
diff --git a/drivers/video/fbdev/vermilion/Makefile b/drivers/video/fbdev/vermilion/Makefile
deleted file mode 100644
index 22e9e4635a00..000000000000
--- a/drivers/video/fbdev/vermilion/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_FB_LE80578) += vmlfb.o
-obj-$(CONFIG_FB_CARILLO_RANCH) += crvml.o
-
-vmlfb-objs := vermilion.o
-crvml-objs := cr_pll.o
diff --git a/drivers/video/fbdev/vermilion/cr_pll.c b/drivers/video/fbdev/vermilion/cr_pll.c
deleted file mode 100644
index 79d42b23d850..000000000000
--- a/drivers/video/fbdev/vermilion/cr_pll.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) Intel Corp. 2007.
- * All Rights Reserved.
- *
- * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- * develop this driver.
- *
- * This file is part of the Carillo Ranch video subsystem driver.
- *
- * Authors:
- * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- * Alan Hourihane <alanh-at-tungstengraphics-dot-com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/errno.h>
-#include <linux/fb.h>
-#include "vermilion.h"
-
-/* The PLL Clock register sits on Host bridge */
-#define CRVML_DEVICE_MCH 0x5001
-#define CRVML_REG_MCHBAR 0x44
-#define CRVML_REG_MCHEN 0x54
-#define CRVML_MCHEN_BIT (1 << 28)
-#define CRVML_MCHMAP_SIZE 4096
-#define CRVML_REG_CLOCK 0xc3c
-#define CRVML_CLOCK_SHIFT 8
-#define CRVML_CLOCK_MASK 0x00000f00
-
-static struct pci_dev *mch_dev;
-static u32 mch_bar;
-static void __iomem *mch_regs_base;
-static u32 saved_clock;
-
-static const unsigned crvml_clocks[] = {
- 6750,
- 13500,
- 27000,
- 29700,
- 37125,
- 54000,
- 59400,
- 74250,
- 120000
- /*
- * There are more clocks, but they are disabled on the CR board.
- */
-};
-
-static const u32 crvml_clock_bits[] = {
- 0x0a,
- 0x09,
- 0x08,
- 0x07,
- 0x06,
- 0x05,
- 0x04,
- 0x03,
- 0x0b
-};
-
-static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks);
-
-static int crvml_sys_restore(struct vml_sys *sys)
-{
- void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
-
- iowrite32(saved_clock, clock_reg);
- ioread32(clock_reg);
-
- return 0;
-}
-
-static int crvml_sys_save(struct vml_sys *sys)
-{
- void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
-
- saved_clock = ioread32(clock_reg);
-
- return 0;
-}
-
-static int crvml_nearest_index(const struct vml_sys *sys, int clock)
-{
- int i;
- int cur_index = 0;
- int cur_diff;
- int diff;
-
- cur_diff = clock - crvml_clocks[0];
- cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
- for (i = 1; i < crvml_num_clocks; ++i) {
- diff = clock - crvml_clocks[i];
- diff = (diff < 0) ? -diff : diff;
- if (diff < cur_diff) {
- cur_index = i;
- cur_diff = diff;
- }
- }
- return cur_index;
-}
-
-static int crvml_nearest_clock(const struct vml_sys *sys, int clock)
-{
- return crvml_clocks[crvml_nearest_index(sys, clock)];
-}
-
-static int crvml_set_clock(struct vml_sys *sys, int clock)
-{
- void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
- int index;
- u32 clock_val;
-
- index = crvml_nearest_index(sys, clock);
-
- if (crvml_clocks[index] != clock)
- return -EINVAL;
-
- clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK;
- clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT;
- iowrite32(clock_val, clock_reg);
- ioread32(clock_reg);
-
- return 0;
-}
-
-static struct vml_sys cr_pll_ops = {
- .name = "Carillo Ranch",
- .save = crvml_sys_save,
- .restore = crvml_sys_restore,
- .set_clock = crvml_set_clock,
- .nearest_clock = crvml_nearest_clock,
-};
-
-static int __init cr_pll_init(void)
-{
- int err;
- u32 dev_en;
-
- mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
- CRVML_DEVICE_MCH, NULL);
- if (!mch_dev) {
- printk(KERN_ERR
- "Could not find Carillo Ranch MCH device.\n");
- return -ENODEV;
- }
-
- pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en);
- if (!(dev_en & CRVML_MCHEN_BIT)) {
- printk(KERN_ERR
- "Carillo Ranch MCH device was not enabled.\n");
- pci_dev_put(mch_dev);
- return -ENODEV;
- }
-
- pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR,
- &mch_bar);
- mch_regs_base =
- ioremap(mch_bar, CRVML_MCHMAP_SIZE);
- if (!mch_regs_base) {
- printk(KERN_ERR
- "Carillo Ranch MCH device was not enabled.\n");
- pci_dev_put(mch_dev);
- return -ENODEV;
- }
-
- err = vmlfb_register_subsys(&cr_pll_ops);
- if (err) {
- printk(KERN_ERR
- "Carillo Ranch failed to initialize vml_sys.\n");
- iounmap(mch_regs_base);
- pci_dev_put(mch_dev);
- return err;
- }
-
- return 0;
-}
-
-static void __exit cr_pll_exit(void)
-{
- vmlfb_unregister_subsys(&cr_pll_ops);
-
- iounmap(mch_regs_base);
- pci_dev_put(mch_dev);
-}
-
-module_init(cr_pll_init);
-module_exit(cr_pll_exit);
-
-MODULE_AUTHOR("Tungsten Graphics Inc.");
-MODULE_DESCRIPTION("Carillo Ranch PLL Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/vermilion/vermilion.c b/drivers/video/fbdev/vermilion/vermilion.c
deleted file mode 100644
index a087b42ca652..000000000000
--- a/drivers/video/fbdev/vermilion/vermilion.c
+++ /dev/null
@@ -1,1175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) Intel Corp. 2007.
- * All Rights Reserved.
- *
- * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- * develop this driver.
- *
- * This file is part of the Vermilion Range fb driver.
- *
- * Authors:
- * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
- * Michel Dänzer <michel-at-tungstengraphics-dot-com>
- * Alan Hourihane <alanh-at-tungstengraphics-dot-com>
- */
-
-#include <linux/aperture.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/pci.h>
-#include <asm/set_memory.h>
-#include <asm/tlbflush.h>
-#include <linux/mmzone.h>
-
-/* #define VERMILION_DEBUG */
-
-#include "vermilion.h"
-
-#define MODULE_NAME "vmlfb"
-
-#define VML_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16)
-
-static struct mutex vml_mutex;
-static struct list_head global_no_mode;
-static struct list_head global_has_mode;
-static struct fb_ops vmlfb_ops;
-static struct vml_sys *subsys = NULL;
-static char *vml_default_mode = "1024x768@60";
-static const struct fb_videomode defaultmode = {
- NULL, 60, 1024, 768, 12896, 144, 24, 29, 3, 136, 6,
- 0, FB_VMODE_NONINTERLACED
-};
-
-static u32 vml_mem_requested = (10 * 1024 * 1024);
-static u32 vml_mem_contig = (4 * 1024 * 1024);
-static u32 vml_mem_min = (4 * 1024 * 1024);
-
-static u32 vml_clocks[] = {
- 6750,
- 13500,
- 27000,
- 29700,
- 37125,
- 54000,
- 59400,
- 74250,
- 120000,
- 148500
-};
-
-static u32 vml_num_clocks = ARRAY_SIZE(vml_clocks);
-
-/*
- * Allocate a contiguous vram area and make its linear kernel map
- * uncached.
- */
-
-static int vmlfb_alloc_vram_area(struct vram_area *va, unsigned max_order,
- unsigned min_order)
-{
- gfp_t flags;
- unsigned long i;
-
- max_order++;
- do {
- /*
- * Really try hard to get the needed memory.
- * We need memory below the first 32MB, so we
- * add the __GFP_DMA flag that guarantees that we are
- * below the first 16MB.
- */
-
- flags = __GFP_DMA | __GFP_HIGH | __GFP_KSWAPD_RECLAIM;
- va->logical =
- __get_free_pages(flags, --max_order);
- } while (va->logical == 0 && max_order > min_order);
-
- if (!va->logical)
- return -ENOMEM;
-
- va->phys = virt_to_phys((void *)va->logical);
- va->size = PAGE_SIZE << max_order;
- va->order = max_order;
-
- /*
- * It seems like __get_free_pages only ups the usage count
- * of the first page. This doesn't work with fault mapping, so
- * up the usage count once more (XXX: should use split_page or
- * compound page).
- */
-
- memset((void *)va->logical, 0x00, va->size);
- for (i = va->logical; i < va->logical + va->size; i += PAGE_SIZE) {
- get_page(virt_to_page(i));
- }
-
- /*
- * Change caching policy of the linear kernel map to avoid
- * mapping type conflicts with user-space mappings.
- */
- set_pages_uc(virt_to_page(va->logical), va->size >> PAGE_SHIFT);
-
- printk(KERN_DEBUG MODULE_NAME
- ": Allocated %ld bytes vram area at 0x%08lx\n",
- va->size, va->phys);
-
- return 0;
-}
-
-/*
- * Free a contiguous vram area and reset its linear kernel map
- * mapping type.
- */
-
-static void vmlfb_free_vram_area(struct vram_area *va)
-{
- unsigned long j;
-
- if (va->logical) {
-
- /*
- * Reset the linear kernel map caching policy.
- */
-
- set_pages_wb(virt_to_page(va->logical),
- va->size >> PAGE_SHIFT);
-
- /*
- * Decrease the usage count on the pages we've used
- * to compensate for upping when allocating.
- */
-
- for (j = va->logical; j < va->logical + va->size;
- j += PAGE_SIZE) {
- (void)put_page_testzero(virt_to_page(j));
- }
-
- printk(KERN_DEBUG MODULE_NAME
- ": Freeing %ld bytes vram area at 0x%08lx\n",
- va->size, va->phys);
- free_pages(va->logical, va->order);
-
- va->logical = 0;
- }
-}
-
-/*
- * Free allocated vram.
- */
-
-static void vmlfb_free_vram(struct vml_info *vinfo)
-{
- int i;
-
- for (i = 0; i < vinfo->num_areas; ++i) {
- vmlfb_free_vram_area(&vinfo->vram[i]);
- }
- vinfo->num_areas = 0;
-}
-
-/*
- * Allocate vram. Currently we try to allocate contiguous areas from the
- * __GFP_DMA zone and puzzle them together. A better approach would be to
- * allocate one contiguous area for scanout and use one-page allocations for
- * offscreen areas. This requires user-space and GPU virtual mappings.
- */
-
-static int vmlfb_alloc_vram(struct vml_info *vinfo,
- size_t requested,
- size_t min_total, size_t min_contig)
-{
- int i, j;
- int order;
- int contiguous;
- int err;
- struct vram_area *va;
- struct vram_area *va2;
-
- vinfo->num_areas = 0;
- for (i = 0; i < VML_VRAM_AREAS; ++i) {
- va = &vinfo->vram[i];
- order = 0;
-
- while (requested > (PAGE_SIZE << order) && order <= MAX_ORDER)
- order++;
-
- err = vmlfb_alloc_vram_area(va, order, 0);
-
- if (err)
- break;
-
- if (i == 0) {
- vinfo->vram_start = va->phys;
- vinfo->vram_logical = (void __iomem *) va->logical;
- vinfo->vram_contig_size = va->size;
- vinfo->num_areas = 1;
- } else {
- contiguous = 0;
-
- for (j = 0; j < i; ++j) {
- va2 = &vinfo->vram[j];
- if (va->phys + va->size == va2->phys ||
- va2->phys + va2->size == va->phys) {
- contiguous = 1;
- break;
- }
- }
-
- if (contiguous) {
- vinfo->num_areas++;
- if (va->phys < vinfo->vram_start) {
- vinfo->vram_start = va->phys;
- vinfo->vram_logical =
- (void __iomem *)va->logical;
- }
- vinfo->vram_contig_size += va->size;
- } else {
- vmlfb_free_vram_area(va);
- break;
- }
- }
-
- if (requested < va->size)
- break;
- else
- requested -= va->size;
- }
-
- if (vinfo->vram_contig_size > min_total &&
- vinfo->vram_contig_size > min_contig) {
-
- printk(KERN_DEBUG MODULE_NAME
- ": Contiguous vram: %ld bytes at physical 0x%08lx.\n",
- (unsigned long)vinfo->vram_contig_size,
- (unsigned long)vinfo->vram_start);
-
- return 0;
- }
-
- printk(KERN_ERR MODULE_NAME
- ": Could not allocate requested minimal amount of vram.\n");
-
- vmlfb_free_vram(vinfo);
-
- return -ENOMEM;
-}
-
-/*
- * Find the GPU to use with our display controller.
- */
-
-static int vmlfb_get_gpu(struct vml_par *par)
-{
- mutex_lock(&vml_mutex);
-
- par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL);
-
- if (!par->gpu) {
- mutex_unlock(&vml_mutex);
- return -ENODEV;
- }
-
- mutex_unlock(&vml_mutex);
-
- if (pci_enable_device(par->gpu) < 0) {
- pci_dev_put(par->gpu);
- return -ENODEV;
- }
-
- return 0;
-}
-
-/*
- * Find a contiguous vram area that contains a given offset from vram start.
- */
-static int vmlfb_vram_offset(struct vml_info *vinfo, unsigned long offset)
-{
- unsigned long aoffset;
- unsigned i;
-
- for (i = 0; i < vinfo->num_areas; ++i) {
- aoffset = offset - (vinfo->vram[i].phys - vinfo->vram_start);
-
- if (aoffset < vinfo->vram[i].size) {
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-/*
- * Remap the MMIO register spaces of the VDC and the GPU.
- */
-
-static int vmlfb_enable_mmio(struct vml_par *par)
-{
- int err;
-
- par->vdc_mem_base = pci_resource_start(par->vdc, 0);
- par->vdc_mem_size = pci_resource_len(par->vdc, 0);
- if (!request_mem_region(par->vdc_mem_base, par->vdc_mem_size, "vmlfb")) {
- printk(KERN_ERR MODULE_NAME
- ": Could not claim display controller MMIO.\n");
- return -EBUSY;
- }
- par->vdc_mem = ioremap(par->vdc_mem_base, par->vdc_mem_size);
- if (par->vdc_mem == NULL) {
- printk(KERN_ERR MODULE_NAME
- ": Could not map display controller MMIO.\n");
- err = -ENOMEM;
- goto out_err_0;
- }
-
- par->gpu_mem_base = pci_resource_start(par->gpu, 0);
- par->gpu_mem_size = pci_resource_len(par->gpu, 0);
- if (!request_mem_region(par->gpu_mem_base, par->gpu_mem_size, "vmlfb")) {
- printk(KERN_ERR MODULE_NAME ": Could not claim GPU MMIO.\n");
- err = -EBUSY;
- goto out_err_1;
- }
- par->gpu_mem = ioremap(par->gpu_mem_base, par->gpu_mem_size);
- if (par->gpu_mem == NULL) {
- printk(KERN_ERR MODULE_NAME ": Could not map GPU MMIO.\n");
- err = -ENOMEM;
- goto out_err_2;
- }
-
- return 0;
-
-out_err_2:
- release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
-out_err_1:
- iounmap(par->vdc_mem);
-out_err_0:
- release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
- return err;
-}
-
-/*
- * Unmap the VDC and GPU register spaces.
- */
-
-static void vmlfb_disable_mmio(struct vml_par *par)
-{
- iounmap(par->gpu_mem);
- release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
- iounmap(par->vdc_mem);
- release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
-}
-
-/*
- * Release and uninit the VDC and GPU.
- */
-
-static void vmlfb_release_devices(struct vml_par *par)
-{
- if (atomic_dec_and_test(&par->refcount)) {
- pci_disable_device(par->gpu);
- pci_disable_device(par->vdc);
- }
-}
-
-/*
- * Free up allocated resources for a device.
- */
-
-static void vml_pci_remove(struct pci_dev *dev)
-{
- struct fb_info *info;
- struct vml_info *vinfo;
- struct vml_par *par;
-
- info = pci_get_drvdata(dev);
- if (info) {
- vinfo = container_of(info, struct vml_info, info);
- par = vinfo->par;
- mutex_lock(&vml_mutex);
- unregister_framebuffer(info);
- fb_dealloc_cmap(&info->cmap);
- vmlfb_free_vram(vinfo);
- vmlfb_disable_mmio(par);
- vmlfb_release_devices(par);
- kfree(vinfo);
- kfree(par);
- mutex_unlock(&vml_mutex);
- }
-}
-
-static void vmlfb_set_pref_pixel_format(struct fb_var_screeninfo *var)
-{
- switch (var->bits_per_pixel) {
- case 16:
- var->blue.offset = 0;
- var->blue.length = 5;
- var->green.offset = 5;
- var->green.length = 5;
- var->red.offset = 10;
- var->red.length = 5;
- var->transp.offset = 15;
- var->transp.length = 1;
- break;
- case 32:
- var->blue.offset = 0;
- var->blue.length = 8;
- var->green.offset = 8;
- var->green.length = 8;
- var->red.offset = 16;
- var->red.length = 8;
- var->transp.offset = 24;
- var->transp.length = 0;
- break;
- default:
- break;
- }
-
- var->blue.msb_right = var->green.msb_right =
- var->red.msb_right = var->transp.msb_right = 0;
-}
-
-/*
- * Device initialization.
- * We initialize one vml_par struct per device and one vml_info
- * struct per pipe. Currently we have only one pipe.
- */
-
-static int vml_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
-{
- struct vml_info *vinfo;
- struct fb_info *info;
- struct vml_par *par;
- int err;
-
- err = aperture_remove_conflicting_pci_devices(dev, "vmlfb");
- if (err)
- return err;
-
- par = kzalloc(sizeof(*par), GFP_KERNEL);
- if (par == NULL)
- return -ENOMEM;
-
- vinfo = kzalloc(sizeof(*vinfo), GFP_KERNEL);
- if (vinfo == NULL) {
- err = -ENOMEM;
- goto out_err_0;
- }
-
- vinfo->par = par;
- par->vdc = dev;
- atomic_set(&par->refcount, 1);
-
- switch (id->device) {
- case VML_DEVICE_VDC:
- if ((err = vmlfb_get_gpu(par)))
- goto out_err_1;
- pci_set_drvdata(dev, &vinfo->info);
- break;
- default:
- err = -ENODEV;
- goto out_err_1;
- }
-
- info = &vinfo->info;
- info->flags = FBINFO_PARTIAL_PAN_OK;
-
- err = vmlfb_enable_mmio(par);
- if (err)
- goto out_err_2;
-
- err = vmlfb_alloc_vram(vinfo, vml_mem_requested,
- vml_mem_contig, vml_mem_min);
- if (err)
- goto out_err_3;
-
- strcpy(info->fix.id, "Vermilion Range");
- info->fix.mmio_start = 0;
- info->fix.mmio_len = 0;
- info->fix.smem_start = vinfo->vram_start;
- info->fix.smem_len = vinfo->vram_contig_size;
- info->fix.type = FB_TYPE_PACKED_PIXELS;
- info->fix.visual = FB_VISUAL_TRUECOLOR;
- info->fix.ypanstep = 1;
- info->fix.xpanstep = 1;
- info->fix.ywrapstep = 0;
- info->fix.accel = FB_ACCEL_NONE;
- info->screen_base = vinfo->vram_logical;
- info->pseudo_palette = vinfo->pseudo_palette;
- info->par = par;
- info->fbops = &vmlfb_ops;
- info->device = &dev->dev;
-
- INIT_LIST_HEAD(&vinfo->head);
- vinfo->pipe_disabled = 1;
- vinfo->cur_blank_mode = FB_BLANK_UNBLANK;
-
- info->var.grayscale = 0;
- info->var.bits_per_pixel = 16;
- vmlfb_set_pref_pixel_format(&info->var);
-
- if (!fb_find_mode
- (&info->var, info, vml_default_mode, NULL, 0, &defaultmode, 16)) {
- printk(KERN_ERR MODULE_NAME ": Could not find initial mode\n");
- }
-
- if (fb_alloc_cmap(&info->cmap, 256, 1) < 0) {
- err = -ENOMEM;
- goto out_err_4;
- }
-
- err = register_framebuffer(info);
- if (err) {
- printk(KERN_ERR MODULE_NAME ": Register framebuffer error.\n");
- goto out_err_5;
- }
-
- printk("Initialized vmlfb\n");
-
- return 0;
-
-out_err_5:
- fb_dealloc_cmap(&info->cmap);
-out_err_4:
- vmlfb_free_vram(vinfo);
-out_err_3:
- vmlfb_disable_mmio(par);
-out_err_2:
- vmlfb_release_devices(par);
-out_err_1:
- kfree(vinfo);
-out_err_0:
- kfree(par);
- return err;
-}
-
-static int vmlfb_open(struct fb_info *info, int user)
-{
- /*
- * Save registers here?
- */
- return 0;
-}
-
-static int vmlfb_release(struct fb_info *info, int user)
-{
- /*
- * Restore registers here.
- */
-
- return 0;
-}
-
-static int vml_nearest_clock(int clock)
-{
-
- int i;
- int cur_index;
- int cur_diff;
- int diff;
-
- cur_index = 0;
- cur_diff = clock - vml_clocks[0];
- cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
- for (i = 1; i < vml_num_clocks; ++i) {
- diff = clock - vml_clocks[i];
- diff = (diff < 0) ? -diff : diff;
- if (diff < cur_diff) {
- cur_index = i;
- cur_diff = diff;
- }
- }
- return vml_clocks[cur_index];
-}
-
-static int vmlfb_check_var_locked(struct fb_var_screeninfo *var,
- struct vml_info *vinfo)
-{
- u32 pitch;
- u64 mem;
- int nearest_clock;
- int clock;
- int clock_diff;
- struct fb_var_screeninfo v;
-
- v = *var;
- clock = PICOS2KHZ(var->pixclock);
-
- if (subsys && subsys->nearest_clock) {
- nearest_clock = subsys->nearest_clock(subsys, clock);
- } else {
- nearest_clock = vml_nearest_clock(clock);
- }
-
- /*
- * Accept a 20% diff.
- */
-
- clock_diff = nearest_clock - clock;
- clock_diff = (clock_diff < 0) ? -clock_diff : clock_diff;
- if (clock_diff > clock / 5) {
-#if 0
- printk(KERN_DEBUG MODULE_NAME ": Diff failure. %d %d\n",clock_diff,clock);
-#endif
- return -EINVAL;
- }
-
- v.pixclock = KHZ2PICOS(nearest_clock);
-
- if (var->xres > VML_MAX_XRES || var->yres > VML_MAX_YRES) {
- printk(KERN_DEBUG MODULE_NAME ": Resolution failure.\n");
- return -EINVAL;
- }
- if (var->xres_virtual > VML_MAX_XRES_VIRTUAL) {
- printk(KERN_DEBUG MODULE_NAME
- ": Virtual resolution failure.\n");
- return -EINVAL;
- }
- switch (v.bits_per_pixel) {
- case 0 ... 16:
- v.bits_per_pixel = 16;
- break;
- case 17 ... 32:
- v.bits_per_pixel = 32;
- break;
- default:
- printk(KERN_DEBUG MODULE_NAME ": Invalid bpp: %d.\n",
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- pitch = ALIGN((var->xres * var->bits_per_pixel) >> 3, 0x40);
- mem = (u64)pitch * var->yres_virtual;
- if (mem > vinfo->vram_contig_size) {
- return -ENOMEM;
- }
-
- switch (v.bits_per_pixel) {
- case 16:
- if (var->blue.offset != 0 ||
- var->blue.length != 5 ||
- var->green.offset != 5 ||
- var->green.length != 5 ||
- var->red.offset != 10 ||
- var->red.length != 5 ||
- var->transp.offset != 15 || var->transp.length != 1) {
- vmlfb_set_pref_pixel_format(&v);
- }
- break;
- case 32:
- if (var->blue.offset != 0 ||
- var->blue.length != 8 ||
- var->green.offset != 8 ||
- var->green.length != 8 ||
- var->red.offset != 16 ||
- var->red.length != 8 ||
- (var->transp.length != 0 && var->transp.length != 8) ||
- (var->transp.length == 8 && var->transp.offset != 24)) {
- vmlfb_set_pref_pixel_format(&v);
- }
- break;
- default:
- return -EINVAL;
- }
-
- *var = v;
-
- return 0;
-}
-
-static int vmlfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-{
- struct vml_info *vinfo = container_of(info, struct vml_info, info);
- int ret;
-
- mutex_lock(&vml_mutex);
- ret = vmlfb_check_var_locked(var, vinfo);
- mutex_unlock(&vml_mutex);
-
- return ret;
-}
-
-static void vml_wait_vblank(struct vml_info *vinfo)
-{
- /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
- mdelay(20);
-}
-
-static void vmlfb_disable_pipe(struct vml_info *vinfo)
-{
- struct vml_par *par = vinfo->par;
-
- /* Disable the MDVO pad */
- VML_WRITE32(par, VML_RCOMPSTAT, 0);
- while (!(VML_READ32(par, VML_RCOMPSTAT) & VML_MDVO_VDC_I_RCOMP)) ;
-
- /* Disable display planes */
- VML_WRITE32(par, VML_DSPCCNTR,
- VML_READ32(par, VML_DSPCCNTR) & ~VML_GFX_ENABLE);
- (void)VML_READ32(par, VML_DSPCCNTR);
- /* Wait for vblank for the disable to take effect */
- vml_wait_vblank(vinfo);
-
- /* Next, disable display pipes */
- VML_WRITE32(par, VML_PIPEACONF, 0);
- (void)VML_READ32(par, VML_PIPEACONF);
-
- vinfo->pipe_disabled = 1;
-}
-
-#ifdef VERMILION_DEBUG
-static void vml_dump_regs(struct vml_info *vinfo)
-{
- struct vml_par *par = vinfo->par;
-
- printk(KERN_DEBUG MODULE_NAME ": Modesetting register dump:\n");
- printk(KERN_DEBUG MODULE_NAME ": \tHTOTAL_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_HTOTAL_A));
- printk(KERN_DEBUG MODULE_NAME ": \tHBLANK_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_HBLANK_A));
- printk(KERN_DEBUG MODULE_NAME ": \tHSYNC_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_HSYNC_A));
- printk(KERN_DEBUG MODULE_NAME ": \tVTOTAL_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_VTOTAL_A));
- printk(KERN_DEBUG MODULE_NAME ": \tVBLANK_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_VBLANK_A));
- printk(KERN_DEBUG MODULE_NAME ": \tVSYNC_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_VSYNC_A));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPCSTRIDE : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPCSTRIDE));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPCSIZE : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPCSIZE));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPCPOS : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPCPOS));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPARB : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPARB));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPCADDR : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPCADDR));
- printk(KERN_DEBUG MODULE_NAME ": \tBCLRPAT_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_BCLRPAT_A));
- printk(KERN_DEBUG MODULE_NAME ": \tCANVSCLR_A : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_CANVSCLR_A));
- printk(KERN_DEBUG MODULE_NAME ": \tPIPEASRC : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_PIPEASRC));
- printk(KERN_DEBUG MODULE_NAME ": \tPIPEACONF : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_PIPEACONF));
- printk(KERN_DEBUG MODULE_NAME ": \tDSPCCNTR : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_DSPCCNTR));
- printk(KERN_DEBUG MODULE_NAME ": \tRCOMPSTAT : 0x%08x\n",
- (unsigned)VML_READ32(par, VML_RCOMPSTAT));
- printk(KERN_DEBUG MODULE_NAME ": End of modesetting register dump.\n");
-}
-#endif
-
-static int vmlfb_set_par_locked(struct vml_info *vinfo)
-{
- struct vml_par *par = vinfo->par;
- struct fb_info *info = &vinfo->info;
- struct fb_var_screeninfo *var = &info->var;
- u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end;
- u32 vtotal, vactive, vblank_start, vblank_end, vsync_start, vsync_end;
- u32 dspcntr;
- int clock;
-
- vinfo->bytes_per_pixel = var->bits_per_pixel >> 3;
- vinfo->stride = ALIGN(var->xres_virtual * vinfo->bytes_per_pixel, 0x40);
- info->fix.line_length = vinfo->stride;
-
- if (!subsys)
- return 0;
-
- htotal =
- var->xres + var->right_margin + var->hsync_len + var->left_margin;
- hactive = var->xres;
- hblank_start = var->xres;
- hblank_end = htotal;
- hsync_start = hactive + var->right_margin;
- hsync_end = hsync_start + var->hsync_len;
-
- vtotal =
- var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
- vactive = var->yres;
- vblank_start = var->yres;
- vblank_end = vtotal;
- vsync_start = vactive + var->lower_margin;
- vsync_end = vsync_start + var->vsync_len;
-
- dspcntr = VML_GFX_ENABLE | VML_GFX_GAMMABYPASS;
- clock = PICOS2KHZ(var->pixclock);
-
- if (subsys->nearest_clock) {
- clock = subsys->nearest_clock(subsys, clock);
- } else {
- clock = vml_nearest_clock(clock);
- }
- printk(KERN_DEBUG MODULE_NAME
- ": Set mode Hfreq : %d kHz, Vfreq : %d Hz.\n", clock / htotal,
- ((clock / htotal) * 1000) / vtotal);
-
- switch (var->bits_per_pixel) {
- case 16:
- dspcntr |= VML_GFX_ARGB1555;
- break;
- case 32:
- if (var->transp.length == 8)
- dspcntr |= VML_GFX_ARGB8888 | VML_GFX_ALPHAMULT;
- else
- dspcntr |= VML_GFX_RGB0888;
- break;
- default:
- return -EINVAL;
- }
-
- vmlfb_disable_pipe(vinfo);
- mb();
-
- if (subsys->set_clock)
- subsys->set_clock(subsys, clock);
- else
- return -EINVAL;
-
- VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
- VML_WRITE32(par, VML_HBLANK_A,
- ((hblank_end - 1) << 16) | (hblank_start - 1));
- VML_WRITE32(par, VML_HSYNC_A,
- ((hsync_end - 1) << 16) | (hsync_start - 1));
- VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1));
- VML_WRITE32(par, VML_VBLANK_A,
- ((vblank_end - 1) << 16) | (vblank_start - 1));
- VML_WRITE32(par, VML_VSYNC_A,
- ((vsync_end - 1) << 16) | (vsync_start - 1));
- VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride);
- VML_WRITE32(par, VML_DSPCSIZE,
- ((var->yres - 1) << 16) | (var->xres - 1));
- VML_WRITE32(par, VML_DSPCPOS, 0x00000000);
- VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT);
- VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000);
- VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000);
- VML_WRITE32(par, VML_PIPEASRC,
- ((var->xres - 1) << 16) | (var->yres - 1));
-
- wmb();
- VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE);
- wmb();
- VML_WRITE32(par, VML_DSPCCNTR, dspcntr);
- wmb();
- VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
- var->yoffset * vinfo->stride +
- var->xoffset * vinfo->bytes_per_pixel);
-
- VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE);
-
- while (!(VML_READ32(par, VML_RCOMPSTAT) &
- (VML_MDVO_VDC_I_RCOMP | VML_MDVO_PAD_ENABLE))) ;
-
- vinfo->pipe_disabled = 0;
-#ifdef VERMILION_DEBUG
- vml_dump_regs(vinfo);
-#endif
-
- return 0;
-}
-
-static int vmlfb_set_par(struct fb_info *info)
-{
- struct vml_info *vinfo = container_of(info, struct vml_info, info);
- int ret;
-
- mutex_lock(&vml_mutex);
- list_move(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode);
- ret = vmlfb_set_par_locked(vinfo);
-
- mutex_unlock(&vml_mutex);
- return ret;
-}
-
-static int vmlfb_blank_locked(struct vml_info *vinfo)
-{
- struct vml_par *par = vinfo->par;
- u32 cur = VML_READ32(par, VML_PIPEACONF);
-
- switch (vinfo->cur_blank_mode) {
- case FB_BLANK_UNBLANK:
- if (vinfo->pipe_disabled) {
- vmlfb_set_par_locked(vinfo);
- }
- VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER);
- (void)VML_READ32(par, VML_PIPEACONF);
- break;
- case FB_BLANK_NORMAL:
- if (vinfo->pipe_disabled) {
- vmlfb_set_par_locked(vinfo);
- }
- VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER);
- (void)VML_READ32(par, VML_PIPEACONF);
- break;
- case FB_BLANK_VSYNC_SUSPEND:
- case FB_BLANK_HSYNC_SUSPEND:
- if (!vinfo->pipe_disabled) {
- vmlfb_disable_pipe(vinfo);
- }
- break;
- case FB_BLANK_POWERDOWN:
- if (!vinfo->pipe_disabled) {
- vmlfb_disable_pipe(vinfo);
- }
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int vmlfb_blank(int blank_mode, struct fb_info *info)
-{
- struct vml_info *vinfo = container_of(info, struct vml_info, info);
- int ret;
-
- mutex_lock(&vml_mutex);
- vinfo->cur_blank_mode = blank_mode;
- ret = vmlfb_blank_locked(vinfo);
- mutex_unlock(&vml_mutex);
- return ret;
-}
-
-static int vmlfb_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct vml_info *vinfo = container_of(info, struct vml_info, info);
- struct vml_par *par = vinfo->par;
-
- mutex_lock(&vml_mutex);
- VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
- var->yoffset * vinfo->stride +
- var->xoffset * vinfo->bytes_per_pixel);
- (void)VML_READ32(par, VML_DSPCADDR);
- mutex_unlock(&vml_mutex);
-
- return 0;
-}
-
-static int vmlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
- u_int transp, struct fb_info *info)
-{
- u32 v;
-
- if (regno >= 16)
- return -EINVAL;
-
- if (info->var.grayscale) {
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
- }
-
- if (info->fix.visual != FB_VISUAL_TRUECOLOR)
- return -EINVAL;
-
- red = VML_TOHW(red, info->var.red.length);
- blue = VML_TOHW(blue, info->var.blue.length);
- green = VML_TOHW(green, info->var.green.length);
- transp = VML_TOHW(transp, info->var.transp.length);
-
- v = (red << info->var.red.offset) |
- (green << info->var.green.offset) |
- (blue << info->var.blue.offset) |
- (transp << info->var.transp.offset);
-
- switch (info->var.bits_per_pixel) {
- case 16:
- ((u32 *) info->pseudo_palette)[regno] = v;
- break;
- case 24:
- case 32:
- ((u32 *) info->pseudo_palette)[regno] = v;
- break;
- }
- return 0;
-}
-
-static int vmlfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
- struct vml_info *vinfo = container_of(info, struct vml_info, info);
- unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
- int ret;
- unsigned long prot;
-
- vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
-
- ret = vmlfb_vram_offset(vinfo, offset);
- if (ret)
- return -EINVAL;
-
- prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
- pgprot_val(vma->vm_page_prot) =
- prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
-
- return vm_iomap_memory(vma, vinfo->vram_start,
- vinfo->vram_contig_size);
-}
-
-static int vmlfb_sync(struct fb_info *info)
-{
- return 0;
-}
-
-static int vmlfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static struct fb_ops vmlfb_ops = {
- .owner = THIS_MODULE,
- .fb_open = vmlfb_open,
- .fb_release = vmlfb_release,
- __FB_DEFAULT_IOMEM_OPS_RDWR,
- .fb_check_var = vmlfb_check_var,
- .fb_set_par = vmlfb_set_par,
- .fb_blank = vmlfb_blank,
- .fb_pan_display = vmlfb_pan_display,
- __FB_DEFAULT_IOMEM_OPS_DRAW,
- .fb_cursor = vmlfb_cursor,
- .fb_sync = vmlfb_sync,
- .fb_mmap = vmlfb_mmap,
- .fb_setcolreg = vmlfb_setcolreg
-};
-
-static const struct pci_device_id vml_ids[] = {
- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, VML_DEVICE_VDC)},
- {0}
-};
-
-static struct pci_driver vmlfb_pci_driver = {
- .name = "vmlfb",
- .id_table = vml_ids,
- .probe = vml_pci_probe,
- .remove = vml_pci_remove,
-};
-
-static void __exit vmlfb_cleanup(void)
-{
- pci_unregister_driver(&vmlfb_pci_driver);
-}
-
-static int __init vmlfb_init(void)
-{
-
-#ifndef MODULE
- char *option = NULL;
-#endif
-
- if (fb_modesetting_disabled("vmlfb"))
- return -ENODEV;
-
-#ifndef MODULE
- if (fb_get_options(MODULE_NAME, &option))
- return -ENODEV;
-#endif
-
- printk(KERN_DEBUG MODULE_NAME ": initializing\n");
- mutex_init(&vml_mutex);
- INIT_LIST_HEAD(&global_no_mode);
- INIT_LIST_HEAD(&global_has_mode);
-
- return pci_register_driver(&vmlfb_pci_driver);
-}
-
-int vmlfb_register_subsys(struct vml_sys *sys)
-{
- struct vml_info *entry;
- struct list_head *list;
- u32 save_activate;
-
- mutex_lock(&vml_mutex);
- if (subsys != NULL) {
- subsys->restore(subsys);
- }
- subsys = sys;
- subsys->save(subsys);
-
- /*
- * We need to restart list traversal for each item, since we
- * release the list mutex in the loop.
- */
-
- list = global_no_mode.next;
- while (list != &global_no_mode) {
- list_del_init(list);
- entry = list_entry(list, struct vml_info, head);
-
- /*
- * First, try the current mode which might not be
- * completely validated with respect to the pixel clock.
- */
-
- if (!vmlfb_check_var_locked(&entry->info.var, entry)) {
- vmlfb_set_par_locked(entry);
- list_add_tail(list, &global_has_mode);
- } else {
-
- /*
- * Didn't work. Try to find another mode,
- * that matches this subsys.
- */
-
- mutex_unlock(&vml_mutex);
- save_activate = entry->info.var.activate;
- entry->info.var.bits_per_pixel = 16;
- vmlfb_set_pref_pixel_format(&entry->info.var);
- if (fb_find_mode(&entry->info.var,
- &entry->info,
- vml_default_mode, NULL, 0, NULL, 16)) {
- entry->info.var.activate |=
- FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
- fb_set_var(&entry->info, &entry->info.var);
- } else {
- printk(KERN_ERR MODULE_NAME
- ": Sorry. no mode found for this subsys.\n");
- }
- entry->info.var.activate = save_activate;
- mutex_lock(&vml_mutex);
- }
- vmlfb_blank_locked(entry);
- list = global_no_mode.next;
- }
- mutex_unlock(&vml_mutex);
-
- printk(KERN_DEBUG MODULE_NAME ": Registered %s subsystem.\n",
- subsys->name ? subsys->name : "unknown");
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(vmlfb_register_subsys);
-
-void vmlfb_unregister_subsys(struct vml_sys *sys)
-{
- struct vml_info *entry, *next;
-
- mutex_lock(&vml_mutex);
- if (subsys != sys) {
- mutex_unlock(&vml_mutex);
- return;
- }
- subsys->restore(subsys);
- subsys = NULL;
- list_for_each_entry_safe(entry, next, &global_has_mode, head) {
- printk(KERN_DEBUG MODULE_NAME ": subsys disable pipe\n");
- vmlfb_disable_pipe(entry);
- list_move_tail(&entry->head, &global_no_mode);
- }
- mutex_unlock(&vml_mutex);
-}
-
-EXPORT_SYMBOL_GPL(vmlfb_unregister_subsys);
-
-module_init(vmlfb_init);
-module_exit(vmlfb_cleanup);
-
-MODULE_AUTHOR("Tungsten Graphics");
-MODULE_DESCRIPTION("Initialization of the Vermilion display devices");
-MODULE_VERSION("1.0.0");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/vermilion/vermilion.h b/drivers/video/fbdev/vermilion/vermilion.h
deleted file mode 100644
index 19cbbe76aba7..000000000000
--- a/drivers/video/fbdev/vermilion/vermilion.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) Intel Corp. 2007.
- * All Rights Reserved.
- *
- * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- * develop this driver.
- *
- * This file is part of the Vermilion Range fb driver.
- *
- * Authors:
- * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
- */
-
-#ifndef _VERMILION_H_
-#define _VERMILION_H_
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/atomic.h>
-#include <linux/mutex.h>
-
-#define VML_DEVICE_GPU 0x5002
-#define VML_DEVICE_VDC 0x5009
-
-#define VML_VRAM_AREAS 3
-#define VML_MAX_XRES 1024
-#define VML_MAX_YRES 768
-#define VML_MAX_XRES_VIRTUAL 1040
-
-/*
- * Display controller registers:
- */
-
-/* Display controller 10-bit color representation */
-
-#define VML_R_MASK 0x3FF00000
-#define VML_R_SHIFT 20
-#define VML_G_MASK 0x000FFC00
-#define VML_G_SHIFT 10
-#define VML_B_MASK 0x000003FF
-#define VML_B_SHIFT 0
-
-/* Graphics plane control */
-#define VML_DSPCCNTR 0x00072180
-#define VML_GFX_ENABLE 0x80000000
-#define VML_GFX_GAMMABYPASS 0x40000000
-#define VML_GFX_ARGB1555 0x0C000000
-#define VML_GFX_RGB0888 0x18000000
-#define VML_GFX_ARGB8888 0x1C000000
-#define VML_GFX_ALPHACONST 0x02000000
-#define VML_GFX_ALPHAMULT 0x01000000
-#define VML_GFX_CONST_ALPHA 0x000000FF
-
-/* Graphics plane start address. Pixel aligned. */
-#define VML_DSPCADDR 0x00072184
-
-/* Graphics plane stride register. */
-#define VML_DSPCSTRIDE 0x00072188
-
-/* Graphics plane position register. */
-#define VML_DSPCPOS 0x0007218C
-#define VML_POS_YMASK 0x0FFF0000
-#define VML_POS_YSHIFT 16
-#define VML_POS_XMASK 0x00000FFF
-#define VML_POS_XSHIFT 0
-
-/* Graphics plane height and width */
-#define VML_DSPCSIZE 0x00072190
-#define VML_SIZE_HMASK 0x0FFF0000
-#define VML_SIZE_HSHIFT 16
-#define VML_SISE_WMASK 0x00000FFF
-#define VML_SIZE_WSHIFT 0
-
-/* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
-#define VML_DSPCGAMLUT 0x00072200
-
-/* Pixel video output configuration register */
-#define VML_PVOCONFIG 0x00061140
-#define VML_CONFIG_BASE 0x80000000
-#define VML_CONFIG_PIXEL_SWAP 0x04000000
-#define VML_CONFIG_DE_INV 0x01000000
-#define VML_CONFIG_HREF_INV 0x00400000
-#define VML_CONFIG_VREF_INV 0x00100000
-#define VML_CONFIG_CLK_INV 0x00040000
-#define VML_CONFIG_CLK_DIV2 0x00010000
-#define VML_CONFIG_ESTRB_INV 0x00008000
-
-/* Pipe A Horizontal total register */
-#define VML_HTOTAL_A 0x00060000
-#define VML_HTOTAL_MASK 0x1FFF0000
-#define VML_HTOTAL_SHIFT 16
-#define VML_HTOTAL_VAL 8192
-#define VML_HACTIVE_MASK 0x000007FF
-#define VML_HACTIVE_SHIFT 0
-#define VML_HACTIVE_VAL 4096
-
-/* Pipe A Horizontal Blank register */
-#define VML_HBLANK_A 0x00060004
-#define VML_HBLANK_END_MASK 0x1FFF0000
-#define VML_HBLANK_END_SHIFT 16
-#define VML_HBLANK_END_VAL 8192
-#define VML_HBLANK_START_MASK 0x00001FFF
-#define VML_HBLANK_START_SHIFT 0
-#define VML_HBLANK_START_VAL 8192
-
-/* Pipe A Horizontal Sync register */
-#define VML_HSYNC_A 0x00060008
-#define VML_HSYNC_END_MASK 0x1FFF0000
-#define VML_HSYNC_END_SHIFT 16
-#define VML_HSYNC_END_VAL 8192
-#define VML_HSYNC_START_MASK 0x00001FFF
-#define VML_HSYNC_START_SHIFT 0
-#define VML_HSYNC_START_VAL 8192
-
-/* Pipe A Vertical total register */
-#define VML_VTOTAL_A 0x0006000C
-#define VML_VTOTAL_MASK 0x1FFF0000
-#define VML_VTOTAL_SHIFT 16
-#define VML_VTOTAL_VAL 8192
-#define VML_VACTIVE_MASK 0x000007FF
-#define VML_VACTIVE_SHIFT 0
-#define VML_VACTIVE_VAL 4096
-
-/* Pipe A Vertical Blank register */
-#define VML_VBLANK_A 0x00060010
-#define VML_VBLANK_END_MASK 0x1FFF0000
-#define VML_VBLANK_END_SHIFT 16
-#define VML_VBLANK_END_VAL 8192
-#define VML_VBLANK_START_MASK 0x00001FFF
-#define VML_VBLANK_START_SHIFT 0
-#define VML_VBLANK_START_VAL 8192
-
-/* Pipe A Vertical Sync register */
-#define VML_VSYNC_A 0x00060014
-#define VML_VSYNC_END_MASK 0x1FFF0000
-#define VML_VSYNC_END_SHIFT 16
-#define VML_VSYNC_END_VAL 8192
-#define VML_VSYNC_START_MASK 0x00001FFF
-#define VML_VSYNC_START_SHIFT 0
-#define VML_VSYNC_START_VAL 8192
-
-/* Pipe A Source Image size (minus one - equal to active size)
- * Programmable while pipe is enabled.
- */
-#define VML_PIPEASRC 0x0006001C
-#define VML_PIPEASRC_HMASK 0x0FFF0000
-#define VML_PIPEASRC_HSHIFT 16
-#define VML_PIPEASRC_VMASK 0x00000FFF
-#define VML_PIPEASRC_VSHIFT 0
-
-/* Pipe A Border Color Pattern register (10 bit color) */
-#define VML_BCLRPAT_A 0x00060020
-
-/* Pipe A Canvas Color register (10 bit color) */
-#define VML_CANVSCLR_A 0x00060024
-
-/* Pipe A Configuration register */
-#define VML_PIPEACONF 0x00070008
-#define VML_PIPE_BASE 0x00000000
-#define VML_PIPE_ENABLE 0x80000000
-#define VML_PIPE_FORCE_BORDER 0x02000000
-#define VML_PIPE_PLANES_OFF 0x00080000
-#define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000
-
-/* Pipe A FIFO setting */
-#define VML_DSPARB 0x00070030
-#define VML_FIFO_DEFAULT 0x00001D9C
-
-/* MDVO rcomp status & pads control register */
-#define VML_RCOMPSTAT 0x00070048
-#define VML_MDVO_VDC_I_RCOMP 0x80000000
-#define VML_MDVO_POWERSAVE_OFF 0x00000008
-#define VML_MDVO_PAD_ENABLE 0x00000004
-#define VML_MDVO_PULLDOWN_ENABLE 0x00000001
-
-struct vml_par {
- struct pci_dev *vdc;
- u64 vdc_mem_base;
- u64 vdc_mem_size;
- char __iomem *vdc_mem;
-
- struct pci_dev *gpu;
- u64 gpu_mem_base;
- u64 gpu_mem_size;
- char __iomem *gpu_mem;
-
- atomic_t refcount;
-};
-
-struct vram_area {
- unsigned long logical;
- unsigned long phys;
- unsigned long size;
- unsigned order;
-};
-
-struct vml_info {
- struct fb_info info;
- struct vml_par *par;
- struct list_head head;
- struct vram_area vram[VML_VRAM_AREAS];
- u64 vram_start;
- u64 vram_contig_size;
- u32 num_areas;
- void __iomem *vram_logical;
- u32 pseudo_palette[16];
- u32 stride;
- u32 bytes_per_pixel;
- atomic_t vmas;
- int cur_blank_mode;
- int pipe_disabled;
-};
-
-/*
- * Subsystem
- */
-
-struct vml_sys {
- char *name;
-
- /*
- * Save / Restore;
- */
-
- int (*save) (struct vml_sys * sys);
- int (*restore) (struct vml_sys * sys);
-
- /*
- * PLL programming;
- */
-
- int (*set_clock) (struct vml_sys * sys, int clock);
- int (*nearest_clock) (const struct vml_sys * sys, int clock);
-};
-
-extern int vmlfb_register_subsys(struct vml_sys *sys);
-extern void vmlfb_unregister_subsys(struct vml_sys *sys);
-
-#define VML_READ32(_par, _offset) \
- (ioread32((_par)->vdc_mem + (_offset)))
-#define VML_WRITE32(_par, _offset, _value) \
- iowrite32(_value, (_par)->vdc_mem + (_offset))
-
-#endif
diff --git a/drivers/video/fbdev/via/via_i2c.c b/drivers/video/fbdev/via/via_i2c.c
index c35e530e0ec9..582502810575 100644
--- a/drivers/video/fbdev/via/via_i2c.c
+++ b/drivers/video/fbdev/via/via_i2c.c
@@ -201,7 +201,6 @@ static int create_i2c_bus(struct i2c_adapter *adapter,
sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
adap_cfg->ioport_index);
adapter->owner = THIS_MODULE;
- adapter->class = I2C_CLASS_DDC;
adapter->algo_data = algo;
if (pdev)
adapter->dev.parent = &pdev->dev;
diff --git a/drivers/video/logo/pnmtologo.c b/drivers/video/logo/pnmtologo.c
index ada5ef6e51b7..2434a25afb64 100644
--- a/drivers/video/logo/pnmtologo.c
+++ b/drivers/video/logo/pnmtologo.c
@@ -249,10 +249,10 @@ static void write_footer(void)
fputs("\n};\n\n", out);
fprintf(out, "const struct linux_logo %s __initconst = {\n", logoname);
fprintf(out, "\t.type\t\t= %s,\n", logo_types[logo_type]);
- fprintf(out, "\t.width\t\t= %d,\n", logo_width);
- fprintf(out, "\t.height\t\t= %d,\n", logo_height);
+ fprintf(out, "\t.width\t\t= %u,\n", logo_width);
+ fprintf(out, "\t.height\t\t= %u,\n", logo_height);
if (logo_type == LINUX_LOGO_CLUT224) {
- fprintf(out, "\t.clutsize\t= %d,\n", logo_clutsize);
+ fprintf(out, "\t.clutsize\t= %u,\n", logo_clutsize);
fprintf(out, "\t.clut\t\t= %s_clut,\n", logoname);
}
fprintf(out, "\t.data\t\t= %s_data\n", logoname);
diff --git a/drivers/video/sticore.c b/drivers/video/sticore.c
index c3765ad6eedf..7115b325817f 100644
--- a/drivers/video/sticore.c
+++ b/drivers/video/sticore.c
@@ -1041,6 +1041,9 @@ static int __init sticore_pa_init(struct parisc_device *dev)
print_pa_hwpath(dev, sti->pa_path);
sticore_check_for_default_sti(sti, sti->pa_path);
+
+ sti->dev = &dev->dev;
+
return 0;
}
@@ -1084,6 +1087,8 @@ static int sticore_pci_init(struct pci_dev *pd, const struct pci_device_id *ent)
pr_warn("Unable to handle STI device '%s'\n", pci_name(pd));
return -ENODEV;
}
+
+ sti->dev = &pd->dev;
#endif /* CONFIG_PCI */
return 0;