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authorLinus Torvalds <torvalds@linux-foundation.org>2015-05-10 02:13:38 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2015-05-10 02:13:38 +0300
commit8f59ae0643b2057ad996ab23488e9be1ba2564f4 (patch)
treec5bc7c71d551455cd3f5d22726ab7ffcef8aff5e /drivers
parent51dfcb076d1e1ce7006aa272cb7c4514740c7e47 (diff)
parentc9d862c48c48883a4327ae82f4a6de1eef928d60 (diff)
downloadlinux-8f59ae0643b2057ad996ab23488e9be1ba2564f4.tar.xz
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann: "A few patches have come up since the merge window. The largest one is a rewrite of the PXA lubbock/mainstone IRQ handling. This was already broken in 2011 by a change to the GPIO code and only noticed now. The other changes contained here are: MAINTAINERS file updates: - Ray Jui and Scott Branden are now co-maintainers for some of the mach-bcm chips, while Christian Daudt and Marc Carino have stepped down. - Andrew Victor is no longer maintaining at91. Instead, Alexandre Belloni now becomes an official maintainer, after having done a bulk of the work for a while. - Baruch Siach, who added the mach-digicolor platform in 4.1 is now listed as maintainer - The git URL for mach-socfpga has changed Bug fixes: - Three bug fixes for new rockchip rk3288 code - A regression fix to make SD card support work on certain ux500 boards - multiple smaller dts fixes for imx, omap, mvebu, and shmobile - a regression fiix for omap3 power consumption - a fix for regression in the ARM CCI bus driver Configuration changes: - more imx platforms are now enabled in multi_v7_defconfig" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) MAINTAINERS: add Conexant Digicolor machines entry MAINTAINERS: socfpga: update the git repo for SoCFPGA ARM: multi_v7_defconfig: Select more FSL SoCs MAINTAINERS: replace an AT91 maintainer drivers: CCI: fix used_mask init in validate_group() bus: omap_l3_noc: Fix master id address decoding for OMAP5 bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance ARM: dts: dra7: Fix efuse register size for ABB ARM: dts: am57xx-beagle-x15: Switch GPIO fan number ARM: dts: am57xx-beagle-x15: Switch UART mux pins ARM: dts: am437x-sk: reduce col-scan-delay-us ARM: dts: am437x-sk: fix for new newhaven display module revision ARM: dts: am57xx-beagle-x15: Fix RTC aliases ARM: dts: am57xx-beagle-x15: Fix IRQ type for mcp7941x ARM: dts: omap3: Add #iommu-cells to isp and iva iommu ARM: omap2plus_defconfig: Enable EXTCON_USB_GPIO ARM: dts: OMAP3-N900: Add microphone bias voltages ARM: OMAP2+: Fix omap off idle power consumption creeping up MAINTAINERS: Update brcmstb entry MAINTAINERS: Remove Christian Daudt for mach-bcm ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/bus/arm-cci.c2
-rw-r--r--drivers/bus/omap_l3_noc.c5
-rw-r--r--drivers/bus/omap_l3_noc.h54
3 files changed, 44 insertions, 17 deletions
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index b854125e4831..5340604b23a4 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -660,7 +660,7 @@ validate_group(struct perf_event *event)
* Initialise the fake PMU. We only need to populate the
* used_mask for the purposes of validation.
*/
- .used_mask = CPU_BITS_NONE,
+ .used_mask = { 0 },
};
if (!validate_event(event->pmu, &fake_pmu, leader))
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 11f7982cbdb3..ebee57d715d2 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -1,7 +1,7 @@
/*
* OMAP L3 Interconnect error handling driver
*
- * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com>
*
@@ -233,7 +233,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
}
static const struct of_device_id l3_noc_match[] = {
- {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
+ {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
+ {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
{},
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index 95254585db86..73431f81da28 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -1,7 +1,7 @@
/*
* OMAP L3 Interconnect error handling driver header
*
- * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* sricharan <r.sricharan@ti.com>
*
@@ -175,16 +175,14 @@ static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
};
-static struct l3_target_data omap_l3_target_data_clk3[] = {
- {0x0100, "EMUSS",},
- {0x0300, "DEBUG SOURCE",},
- {0x0, "HOST CLK3",},
+static struct l3_target_data omap4_l3_target_data_clk3[] = {
+ {0x0100, "DEBUGSS",},
};
-static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
+static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
.offset = 0x0200,
- .l3_targ = omap_l3_target_data_clk3,
- .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
+ .l3_targ = omap4_l3_target_data_clk3,
+ .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
};
static struct l3_masters_data omap_l3_masters[] = {
@@ -215,21 +213,49 @@ static struct l3_masters_data omap_l3_masters[] = {
{ 0x32, "USBHOSTFS"}
};
-static struct l3_flagmux_data *omap_l3_flagmux[] = {
+static struct l3_flagmux_data *omap4_l3_flagmux[] = {
&omap_l3_flagmux_clk1,
&omap_l3_flagmux_clk2,
- &omap_l3_flagmux_clk3,
+ &omap4_l3_flagmux_clk3,
};
-static const struct omap_l3 omap_l3_data = {
- .l3_flagmux = omap_l3_flagmux,
- .num_modules = ARRAY_SIZE(omap_l3_flagmux),
+static const struct omap_l3 omap4_l3_data = {
+ .l3_flagmux = omap4_l3_flagmux,
+ .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
.l3_masters = omap_l3_masters,
.num_masters = ARRAY_SIZE(omap_l3_masters),
/* The 6 MSBs of register field used to distinguish initiator */
.mst_addr_mask = 0xFC,
};
+/* OMAP5 data */
+static struct l3_target_data omap5_l3_target_data_clk3[] = {
+ {0x0100, "L3INSTR",},
+ {0x0300, "DEBUGSS",},
+ {0x0, "HOSTCLK3",},
+};
+
+static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
+ .offset = 0x0200,
+ .l3_targ = omap5_l3_target_data_clk3,
+ .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
+};
+
+static struct l3_flagmux_data *omap5_l3_flagmux[] = {
+ &omap_l3_flagmux_clk1,
+ &omap_l3_flagmux_clk2,
+ &omap5_l3_flagmux_clk3,
+};
+
+static const struct omap_l3 omap5_l3_data = {
+ .l3_flagmux = omap5_l3_flagmux,
+ .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
+ .l3_masters = omap_l3_masters,
+ .num_masters = ARRAY_SIZE(omap_l3_masters),
+ /* The 6 MSBs of register field used to distinguish initiator */
+ .mst_addr_mask = 0x7E0,
+};
+
/* DRA7 data */
static struct l3_target_data dra_l3_target_data_clk1[] = {
{0x2a00, "AES1",},
@@ -274,7 +300,7 @@ static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
static struct l3_target_data dra_l3_target_data_clk2[] = {
{0x0, "HOST CLK1",},
- {0x0, "HOST CLK2",},
+ {0x800000, "HOST CLK2",},
{0xdead, L3_TARGET_NOT_SUPPORTED,},
{0x3400, "SHA2_2",},
{0x0900, "BB2D",},