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authorLinus Torvalds <torvalds@linux-foundation.org>2017-10-21 01:17:43 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2017-10-21 01:17:43 +0300
commit545ea16f7c42969f94c769d0c2267cf4a65e5850 (patch)
treeba2835f51f3a3f42c309fc18e1381432ea3f171c /drivers
parent1c9fec470b81ca5e89391c20a11ead31a1e9314b (diff)
parent6bf99a6cb69f78de0083b76a7c033918f853f580 (diff)
downloadlinux-545ea16f7c42969f94c769d0c2267cf4a65e5850.tar.xz
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann: "Here is another set of bugfixes for ARM SoCs, mostly harmless: - a boot regression fix on ux500 - PCIe interrupts on NXP i.MX7 and on Marvell Armada 7K/8K were wired up wrong, in different ways - Armada XP support for large memory never worked - the socfpga reset controller now builds on 64-bit - minor device tree corrections on gemini, mvebu, r-pi 3, rockchip and at91" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: ux500: Fix regression while init PM domains ARM: dts: fix PCLK name on Gemini and MOXA ART arm64: dts: rockchip: fix typo in iommu nodes arm64: dts: rockchip: correct vqmmc voltage for rk3399 platforms ARM: dts: imx7d: Invert legacy PCI irq mapping bus: mbus: fix window size calculation for 4GB windows ARM: dts: at91: sama5d2: add ADC hw trigger edge type ARM: dts: at91: sama5d2_xplained: enable ADTRG pin ARM: dts: at91: at91-sama5d27_som1: fix PHY ID ARM: dts: bcm283x: Fix console path on RPi3 reset: socfpga: fix for 64-bit compilation ARM: dts: Fix I2C repeated start issue on Armada-38x arm64: dts: marvell: fix interrupt-map property for Armada CP110 PCIe controller arm64: dts: salvator-common: add 12V regulator to backlight ARM: dts: sun6i: Fix endpoint IDs in second display pipeline arm64: allwinner: a64: pine64: Use dcdc1 regulator for mmc0
Diffstat (limited to 'drivers')
-rw-r--r--drivers/bus/mvebu-mbus.c2
-rw-r--r--drivers/reset/reset-socfpga.c17
2 files changed, 11 insertions, 8 deletions
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index c7f396903184..70db4d5638a6 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -720,7 +720,7 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
if (mbus->hw_io_coherency)
w->mbus_attr |= ATTR_HW_COHERENCY;
w->base = base & DDR_BASE_CS_LOW_MASK;
- w->size = (size | ~DDR_SIZE_MASK) + 1;
+ w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
}
}
mvebu_mbus_dram_info.num_cs = cs;
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index c60904ff40b8..3907bbc9c6cf 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -40,8 +40,9 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
struct socfpga_reset_data *data = container_of(rcdev,
struct socfpga_reset_data,
rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
@@ -61,8 +62,9 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
struct socfpga_reset_data,
rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
@@ -81,8 +83,9 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
{
struct socfpga_reset_data *data = container_of(rcdev,
struct socfpga_reset_data, rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
u32 reg;
reg = readl(data->membase + (bank * BANK_INCREMENT));
@@ -132,7 +135,7 @@ static int socfpga_reset_probe(struct platform_device *pdev)
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
+ data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
data->rcdev.ops = &socfpga_reset_ops;
data->rcdev.of_node = pdev->dev.of_node;