diff options
| author | David S. Miller <davem@davemloft.net> | 2021-10-04 15:50:05 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-10-04 15:50:05 +0300 |
| commit | 1660034361904dfcb82714aa48615a9b66462ee6 (patch) | |
| tree | a57d0385bf608dfea11fc8ef77685cd16d244eb7 /drivers | |
| parent | 23b08260481ca552180130bbef0f3a60df4c092e (diff) | |
| parent | 14ad41c74f6be0bfaf5202b7e49254e2482da56f (diff) | |
| download | linux-1660034361904dfcb82714aa48615a9b66462ee6.tar.xz | |
Merge branch 'phy-10g-mode-helper'
Russell King says:
====================
Add phylink helper for 10G modes
During the last cycle, there was discussion about adding a helper
to set the 10G link modes for phylink, which resulted in these two
patches introduce such a helper.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/cadence/macb_main.c | 7 | ||||
| -rw-r--r-- | drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 | ||||
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 | ||||
| -rw-r--r-- | drivers/net/phy/phylink.c | 11 |
4 files changed, 14 insertions, 18 deletions
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index e2730b3e1a57..b58297aeb793 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -547,13 +547,8 @@ static void macb_validate(struct phylink_config *config, if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE && (state->interface == PHY_INTERFACE_MODE_NA || state->interface == PHY_INTERFACE_MODE_10GBASER)) { - phylink_set(mask, 10000baseCR_Full); - phylink_set(mask, 10000baseER_Full); + phylink_set_10g_modes(mask); phylink_set(mask, 10000baseKR_Full); - phylink_set(mask, 10000baseLR_Full); - phylink_set(mask, 10000baseLRM_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseT_Full); if (state->interface != PHY_INTERFACE_MODE_NA) goto out; } diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c index 543c1f202420..ef8f0a055024 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c @@ -139,12 +139,7 @@ static void dpaa2_mac_validate(struct phylink_config *config, case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_USXGMII: - phylink_set(mask, 10000baseT_Full); - phylink_set(mask, 10000baseCR_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseLR_Full); - phylink_set(mask, 10000baseLRM_Full); - phylink_set(mask, 10000baseER_Full); + phylink_set_10g_modes(mask); if (state->interface == PHY_INTERFACE_MODE_10GBASER) break; phylink_set(mask, 5000baseT_Full); diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 94ea6dd91b74..3197526455d9 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -6301,12 +6301,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config, case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_NA: if (mvpp2_port_supports_xlg(port)) { - phylink_set(mask, 10000baseT_Full); - phylink_set(mask, 10000baseCR_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseLR_Full); - phylink_set(mask, 10000baseLRM_Full); - phylink_set(mask, 10000baseER_Full); + phylink_set_10g_modes(mask); phylink_set(mask, 10000baseKR_Full); } if (state->interface != PHY_INTERFACE_MODE_NA) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 5a58c77d0002..b32774fd65f8 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -132,6 +132,17 @@ void phylink_set_port_modes(unsigned long *mask) } EXPORT_SYMBOL_GPL(phylink_set_port_modes); +void phylink_set_10g_modes(unsigned long *mask) +{ + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 10000baseCR_Full); + phylink_set(mask, 10000baseSR_Full); + phylink_set(mask, 10000baseLR_Full); + phylink_set(mask, 10000baseLRM_Full); + phylink_set(mask, 10000baseER_Full); +} +EXPORT_SYMBOL_GPL(phylink_set_10g_modes); + static int phylink_is_empty_linkmode(const unsigned long *linkmode) { __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp) = { 0, }; |