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authorRobin Holt <holt@sgi.com>2005-11-11 18:35:43 +0300
committerTony Luck <tony.luck@intel.com>2005-11-11 20:37:29 +0300
commit837cd0bdf54dd954cd6aa43d250f75ab5db79617 (patch)
treeef28b91f1ac8c1c9f4244da9be1f994306ef4070 /include/asm-ia64/page.h
parentd12eb7e11cf30c30f639b2093735af2ac177830b (diff)
downloadlinux-837cd0bdf54dd954cd6aa43d250f75ab5db79617.tar.xz
[IA64] 4-level page tables
This patch introduces 4-level page tables to ia64. I have run some benchmarks and found nothing interesting. Performance has consistently fallen within the noise range. It also introduces a config option (setting the default to 3 levels). The config option prevents having 4 level page tables with 64k base page size. Signed-off-by: Robin Holt <holt@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/page.h')
-rw-r--r--include/asm-ia64/page.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 9d41548b7fef..9dd9da105278 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -47,8 +47,6 @@
#define PERCPU_PAGE_SHIFT 16 /* log2() of max. size of per-CPU area */
#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
-#define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */
-
#ifdef CONFIG_HUGETLB_PAGE
# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE)
@@ -175,11 +173,17 @@ get_order (unsigned long size)
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
+#ifdef CONFIG_PGTABLE_4
+ typedef struct { unsigned long pud; } pud_t;
+#endif
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
# define pte_val(x) ((x).pte)
# define pmd_val(x) ((x).pmd)
+#ifdef CONFIG_PGTABLE_4
+# define pud_val(x) ((x).pud)
+#endif
# define pgd_val(x) ((x).pgd)
# define pgprot_val(x) ((x).pgprot)