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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-21 19:50:57 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-21 19:50:57 +0400
commit0ddaa974258a4cde9a06c079bfd7863644e10d31 (patch)
treed0b70cb3f82399cb0c48e3c74d3b76639c624290 /include/drm
parent007b703b3ed74e9af9c0576e7698ccda0170d370 (diff)
parentcc3e06a57d4314ca0582fcf7d6b56dea5ca11f77 (diff)
downloadlinux-0ddaa974258a4cde9a06c079bfd7863644e10d31.tar.xz
Merge branch 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux
Pull radeon sun/hainan support from Dave Airlie: "Since I know its outside the merge window, but since this is new hw I thought I'd try and provoke the new hw exception, it just fills in the blanks in the driver for the new AMD sun and hainan chipsets." * 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux: drm/radeon: add Hainan pci ids drm/radeon: add golden register settings for Hainan (v2) drm/radeon: sun/hainan chips do not have UVD (v2) drm/radeon: track which asics have UVD drm/radeon: radeon-asic updates for Hainan drm/radeon: fill in ucode loading support for Hainan drm/radeon: don't touch DCE or VGA regs on Hainan (v3) drm/radeon: fill in GPU init for Hainan (v2) drm/radeon: add chip family for Hainan
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_pciids.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index c2af598f701d..bb1bc485390b 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -152,6 +152,12 @@
{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \