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authorDave Airlie <airlied@redhat.com>2024-02-15 23:52:03 +0300
committerDave Airlie <airlied@redhat.com>2024-02-15 23:52:04 +0300
commitb13cfb445c91837db967148222374f591fbdb20c (patch)
tree8b20e0233a2f3d0c1e96c334a2cf89364fa033ec /include/drm
parentb344e64fbda303b767a3844ee739a596a9c3679e (diff)
parent449c2d5948ba8c784dcbc5c67df1d8c54748caa4 (diff)
downloadlinux-b13cfb445c91837db967148222374f591fbdb20c.tar.xz
Merge tag 'drm-intel-next-2024-02-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 feature pull for v6.9: Features and functionality: - Early transport for panel replay and PSR (Jouni) - New ARL PCI IDs (Matt) - DP TPS4 PHY test pattern support (Khaled) Refactoring and cleanups: - Unify and improve VSC SDP for PSR and non-PSR cases (Jouni) - Refactor memory regions and improve debug logging (Ville) - Rework global state serialization (Ville) - Remove unused CDCLK divider fields (Gustavo) - Unify HDCP connector logging format (Jani) - Use display instead of graphics version in display code (Jani) - Move VBT and opregion debugfs next to the implementation (Jani) - Abstract opregion interface, use opaque type (Jani) Fixes: - Fix MTL stolen memory access (Ville) - Fix initial display plane readout for MTL (Ville) - Fix HPD handling during driver init/shutdown (Imre) - Cursor vblank evasion fixes (Ville) - Various VSC SDP fixes (Jouni) - Allow PSR mode changes without full modeset (Jouni) - Fix CDCLK sanitization on module load for Xe2_LPD (Gustavo) - Fix the max DSC bpc supported by the source (Ankit) - Add missing LNL ALPM AUX wake configuration (Jouni) - Cx0 PHY state readout and verify fixes (Mika) - Fix PSR (panel replay) debugfs for MST connectors (Imre) - Fail HDCP repeater authentication if Type1 device not present (Suraj) - Ratelimit debug logging in vm_fault_ttm (Nirmoy) - Use a fake PCH for MTL because south display is not on the PCH (Haridhar) - Disable DSB for Xe driver for now (José) - Fix some LNL display register changes (Lucas) - Fix build on ChromeOS (Paz Zcharya) - Preserve current shared DPLL for fastsets on Type-C ports (Ville) - Fix state checker warnings for MG/TC/TBT PLLs (Ville) - Fix HDCP repeater ctl register value on errors (Jani) - Allow FBC with CCS modifiers on SKL+ (Ville) - Fix HDCP GGTT pinning (Ville) DRM core changes: - Add ratelimited drm dbg print (Nirmoy) - DPCD PSR early transport macro (Jouni) Merges: - Backmerge drm-next to bring Xe driver to drm-intel-next (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87cyt8cxsh.fsf@intel.com
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/display/drm_dp.h1
-rw-r--r--include/drm/drm_print.h3
-rw-r--r--include/drm/i915_pciids.h3
3 files changed, 7 insertions, 0 deletions
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 3731828825bd..281afff6ee4e 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -718,6 +718,7 @@
# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
+# define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */
#define DP_ADAPTER_CTRL 0x1a0
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index dd4883df876a..5ed26a702e3e 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -602,6 +602,9 @@ void __drm_err(const char *format, ...);
drm_dev_printk(drm_ ? drm_->dev : NULL, KERN_DEBUG, fmt, ## __VA_ARGS__); \
})
+#define drm_dbg_ratelimited(drm, fmt, ...) \
+ __DRM_DEFINE_DBG_RATELIMITED(DRIVER, drm, fmt, ## __VA_ARGS__)
+
#define drm_dbg_kms_ratelimited(drm, fmt, ...) \
__DRM_DEFINE_DBG_RATELIMITED(KMS, drm, fmt, ## __VA_ARGS__)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index fcf1849aa47c..07779a11758e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -751,10 +751,13 @@
/* MTL */
#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
+ INTEL_VGA_DEVICE(0x7D41, info), \
INTEL_VGA_DEVICE(0x7D45, info), \
+ INTEL_VGA_DEVICE(0x7D51, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7D67, info), \
+ INTEL_VGA_DEVICE(0x7DD1, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
#endif /* _I915_PCIIDS_H */