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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-20 20:32:50 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-25 07:46:09 +0300 |
| commit | 2aae5eaa941e356b5f6e78c207c7dc3a93286622 (patch) | |
| tree | 1f664f1ce3568e881ea74804f57d82d3622be49d /include/dt-bindings/reset | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| download | linux-2aae5eaa941e356b5f6e78c207c7dc3a93286622.tar.xz | |
dt-bindings: clock: Add SM8350 VIDEOCC
SM8350, like most recent higher-end chips has a separate clock
controller block just for the Venus IP. Document it.
The binding was separated as the driver, unlike the earlier ones, doesn't
expect clock-names to keep it easier to maintain.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/qcom,sm8350-videocc.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-bindings/reset/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..cd356b207a4a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8350-videocc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H + +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#endif |