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authorArnd Bergmann <arnd@arndb.de>2021-12-20 17:37:23 +0300
committerArnd Bergmann <arnd@arndb.de>2021-12-20 17:37:24 +0300
commitb87cd3759d9d45cbf763bb592129e02871e69261 (patch)
tree9a820277aa63ce3acd38e93640c38c899c887a32 /include/dt-bindings
parent79309f5bf43d31b13c657002b6eb728a0ec9cf79 (diff)
parentc9059a6bb993db31cd85f3a4081766af9e61be40 (diff)
downloadlinux-b87cd3759d9d45cbf763bb592129e02871e69261.tar.xz
Merge tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.17-rc1 This contains a bunch of json-schema conversions for various Tegra- related DT bindings and additions for new SoC and board support. * tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits) media: dt: bindings: tegra-vde: Document OPP and power domain media: dt: bindings: tegra-vde: Convert to schema dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D dt-bindings: host1x: Document OPP and power domain properties dt-bindings: clock: tegra-car: Document new clock sub-nodes dt-bindings: ARM: tegra: Document Pegatron Chagall dt-bindings: ARM: tegra: Document ASUS Transformers dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties dt-bindings: serial: Document Tegra234 TCU dt-bindings: serial: tegra-tcu: Convert to json-schema dt-bindings: thermal: tegra186-bpmp: Convert to json-schema dt-bindings: firmware: tegra: Convert to json-schema dt-bindings: tegra: pmc: Convert to json-schema dt-bindings: serial: 8250: Document Tegra234 UART dt-bindings: mmc: tegra: Document Tegra234 SDHCI dt-bindings: fuse: tegra: Document Tegra234 FUSE dt-bindings: fuse: tegra: Convert to json-schema dt-bindings: rtc: tegra: Document Tegra234 RTC dt-bindings: rtc: tegra: Convert to json-schema dt-bindings: mailbox: tegra: Document Tegra234 HSP ... Link: https://lore.kernel.org/r/20211217162253.1801077-3-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/tegra234-clock.h26
-rw-r--r--include/dt-bindings/memory/tegra234-mc.h32
-rw-r--r--include/dt-bindings/reset/tegra234-reset.h12
3 files changed, 65 insertions, 5 deletions
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 2c82072950ee..8d7e66e1b6ef 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -4,11 +4,31 @@
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
+/**
+ * @file
+ * @defgroup bpmp_clock_ids Clock ID's
+ * @{
+ */
+/**
+ * @brief controls the EMC clock frequency.
+ * @details Doing a clk_set_rate on this clock will select the
+ * appropriate clock source, program the source rate and execute a
+ * specific sequence to switch to the new clock source for both memory
+ * controllers. This can be used to control the balance between memory
+ * throughput and memory controller power.
+ */
+#define TEGRA234_CLK_EMC 31U
/** @brief output of gate CLK_ENB_FUSE */
-#define TEGRA234_CLK_FUSE 40
+#define TEGRA234_CLK_FUSE 40U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
-#define TEGRA234_CLK_SDMMC4 123
+#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
-#define TEGRA234_CLK_UARTA 155
+#define TEGRA234_CLK_UARTA 155U
+/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
+#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
+#define TEGRA234_CLK_PLLC4 237U
+/** @brief 32K input clock provided by PMIC */
+#define TEGRA234_CLK_CLK_32K 289U
#endif
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
new file mode 100644
index 000000000000..2662f70c15c6
--- /dev/null
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
+
+/* special clients */
+#define TEGRA234_SID_INVALID 0x00
+#define TEGRA234_SID_PASSTHROUGH 0x7f
+
+
+/* NISO1 stream IDs */
+#define TEGRA234_SID_SDMMC4 0x02
+#define TEGRA234_SID_BPMP 0x10
+
+/*
+ * memory client IDs
+ */
+
+/* sdmmcd memory read client */
+#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
+/* sdmmcd memory write client */
+#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
+/* BPMP read client */
+#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
+/* BPMP write client */
+#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
+/* BPMPDMA read client */
+#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
+/* BPMPDMA write client */
+#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
+
+#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index b3c63be06d2d..50e13bced642 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -4,7 +4,15 @@
#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
#define DT_BINDINGS_RESET_TEGRA234_RESET_H
-#define TEGRA234_RESET_SDMMC4 85
-#define TEGRA234_RESET_UARTA 100
+/**
+ * @file
+ * @defgroup bpmp_reset_ids Reset ID's
+ * @brief Identifiers for Resets controllable by firmware
+ * @{
+ */
+#define TEGRA234_RESET_SDMMC4 85U
+#define TEGRA234_RESET_UARTA 100U
+
+/** @} */
#endif