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authorAndrew Murray <andrew.murray@arm.com>2019-06-17 22:01:05 +0300
committerMarc Zyngier <marc.zyngier@arm.com>2019-07-05 15:56:22 +0300
commit80f393a23be68e2f8a0f74258d6155438c200bbd (patch)
treec07e0e47ad5c14a8cbfef8cfe9a0763faf153254 /include/kvm/arm_pmu.h
parent218907cbc2b82419c70180610163c987d4764b27 (diff)
downloadlinux-80f393a23be68e2f8a0f74258d6155438c200bbd.tar.xz
KVM: arm/arm64: Support chained PMU counters
ARMv8 provides support for chained PMU counters, where an event type of 0x001E is set for odd-numbered counters, the event counter will increment by one for each overflow of the preceding even-numbered counter. Let's emulate this in KVM by creating a 64 bit perf counter when a user chains two emulated counters together. For chained events we only support generating an overflow interrupt on the high counter. We use the attributes of the low counter to determine the attributes of the perf event. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Julien Thierry <julien.thierry@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/kvm/arm_pmu.h')
-rw-r--r--include/kvm/arm_pmu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 48a15d4b820e..16c769a7f979 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -11,6 +11,7 @@
#include <asm/perf_event.h>
#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
+#define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)
#ifdef CONFIG_KVM_ARM_PMU
@@ -22,6 +23,7 @@ struct kvm_pmc {
struct kvm_pmu {
int irq_num;
struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
+ DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
bool ready;
bool created;
bool irq_level;