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authorShannon Zhao <shannon.zhao@linaro.org>2015-12-08 10:29:06 +0300
committerMarc Zyngier <marc.zyngier@arm.com>2016-02-29 21:34:20 +0300
commit051ff581ce70e822729e9474941f3c206cbf7436 (patch)
tree3df20342cf7ae5df7afaed1116f3dd242cccefe2 /include/kvm
parenta86b5505304404dc5fc5e62a6dc294706e525003 (diff)
downloadlinux-051ff581ce70e822729e9474941f3c206cbf7436.tar.xz
arm64: KVM: Add access handler for event counter register
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big endian. When reading these registers, return the sum of register value and the value perf event counts. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/kvm')
-rw-r--r--include/kvm/arm_pmu.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 8157fe5bcbb0..bcb769805839 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -23,6 +23,8 @@
#include <linux/perf_event.h>
#include <asm/perf_event.h>
+#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
+
struct kvm_pmc {
u8 idx; /* index into the pmu->pmc array */
struct perf_event *perf_event;
@@ -36,11 +38,20 @@ struct kvm_pmu {
};
#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
+u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
+void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
#else
struct kvm_pmu {
};
#define kvm_arm_pmu_v3_ready(v) (false)
+static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
+ u64 select_idx)
+{
+ return 0;
+}
+static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
+ u64 select_idx, u64 val) {}
#endif
#endif