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authorZhang, Yanmin <yanmin.zhang@intel.com>2006-07-31 11:21:33 +0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-09-27 04:43:53 +0400
commit6c2b374d74857e892080ee726184ec1d15e7d4e4 (patch)
treec107532c288bcede80e45ebc3e46292bfaf0cea2 /include/linux/aer.h
parent48408157ebf5b2c6dc1e04ba5d258012f6a7f356 (diff)
downloadlinux-6c2b374d74857e892080ee726184ec1d15e7d4e4.tar.xz
PCI-Express AER implemetation: AER core and aerdriver
Patch 3 implements the core part of PCI-Express AER and aerdrv port service driver. When a root port service device is probed, the aerdrv will call request_irq to register irq handler for AER error interrupt. When a device sends an PCI-Express error message to the root port, the root port will trigger an interrupt, by either MSI or IO-APIC, then kernel would run the irq handler. The handler collects root error status register and schedules a work. The work will call the core part to process the error based on its type (Correctable/non-fatal/fatal). As for Correctable errors, the patch chooses to just clear the correctable error status register of the device. As for the non-fatal error, the patch follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. As for the fatal error, the patch resets the pci-express link and follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/aer.h')
-rw-r--r--include/linux/aer.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/include/linux/aer.h b/include/linux/aer.h
new file mode 100644
index 000000000000..402e178b38eb
--- /dev/null
+++ b/include/linux/aer.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2006 Intel Corp.
+ * Tom Long Nguyen (tom.l.nguyen@intel.com)
+ * Zhang Yanmin (yanmin.zhang@intel.com)
+ */
+
+#ifndef _AER_H_
+#define _AER_H_
+
+#if defined(CONFIG_PCIEAER)
+/* pci-e port driver needs this function to enable aer */
+extern int pci_enable_pcie_error_reporting(struct pci_dev *dev);
+extern int pci_find_aer_capability(struct pci_dev *dev);
+extern int pci_disable_pcie_error_reporting(struct pci_dev *dev);
+extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
+#else
+#define pci_enable_pcie_error_reporting(dev) do { } while (0)
+#define pci_find_aer_capability(dev) do { } while (0)
+#define pci_disable_pcie_error_reporting(dev) do { } while (0)
+#define pci_cleanup_aer_uncorrect_error_status(dev) do { } while (0)
+#endif
+
+#endif //_AER_H_
+