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authorMathieu Poirier <mathieu.poirier@linaro.org>2016-02-18 03:52:01 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-02-21 01:11:01 +0300
commit0bcbf2e30ff2271b54f54c8697a185f7d86ec6e4 (patch)
tree59ba04e18f5b0fb65213494800a6b591513767be /include/linux/coresight-pmu.h
parent2997aa4063d97fdb39450c6078bd81a7b0504f22 (diff)
downloadlinux-0bcbf2e30ff2271b54f54c8697a185f7d86ec6e4.tar.xz
coresight: etm-perf: new PMU driver for ETM tracers
Perf is a well known and used tool for performance monitoring and much more. A such it is an ideal candidate for integration with coresight based HW tracing. This patch introduces a PMU that represent a coresight tracer to the Perf core. Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/coresight-pmu.h')
-rw-r--r--include/linux/coresight-pmu.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
new file mode 100644
index 000000000000..6c5386b23b10
--- /dev/null
+++ b/include/linux/coresight-pmu.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_CORESIGHT_PMU_H
+#define _LINUX_CORESIGHT_PMU_H
+
+#define CORESIGHT_ETM_PMU_NAME "cs_etm"
+
+/* ETMv3.5/PTM's ETMCR config bit */
+#define ETM_OPT_CYCACC 12
+#define ETM_OPT_TS 28
+
+#endif