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authorHeyi Guo <guoheyi@huawei.com>2019-11-30 10:38:49 +0300
committerMarc Zyngier <maz@kernel.org>2020-03-21 12:40:47 +0300
commitb2cb11f4f7643255b7703c0fcabc31a8ec478f3a (patch)
tree9f026900ded7539d9dc34386bbb6898e5a55b2c8 /include/linux/irqchip
parent486562da598c59e9f835b551d7cf19507de2d681 (diff)
downloadlinux-b2cb11f4f7643255b7703c0fcabc31a8ec478f3a.tar.xz
irqchip/gic-v4: Use Inner-Shareable attributes for virtual pending tables
There is no special reason to set virtual LPI pending table as non-shareable. If we choose to hard code the shareability without probing, Inner-Shareable is likely to be a better choice, as the VPEs can move around and benefit from having the redistributors snooping each other's cache, if that's something they can do. Furthermore, Hisilicon hip08 ends up with unspecified errors when mixing shareability attributes. So let's move to IS attributes for the VPT. This has also been tested on D05 and didn't show any regression. Signed-off-by: Heyi Guo <guoheyi@huawei.com> [maz: rewrote commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20191130073849.38378-1-guoheyi@huawei.com
Diffstat (limited to 'include/linux/irqchip')
-rw-r--r--include/linux/irqchip/arm-gic-v3.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 83439bfb6c5b..85b105f6dc36 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -320,6 +320,9 @@
#define GICR_VPENDBASER_NonShareable \
GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
+#define GICR_VPENDBASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
+
#define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
#define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
#define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)