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| author | Maher Sanalla <msanalla@nvidia.com> | 2022-11-28 19:00:17 +0300 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2023-01-11 08:24:39 +0300 |
| commit | 8d231dbc3b10155727bcfa9e543d397ad357f14f (patch) | |
| tree | d5ce74c6795a57eab9510deb6cdd68f0e66c2bc1 /include/linux/mlx5/driver.h | |
| parent | a6f536063b69102adf3588fbc0bb4f08d6c8cb82 (diff) | |
| download | linux-8d231dbc3b10155727bcfa9e543d397ad357f14f.tar.xz | |
net/mlx5: Expose shared buffer registers bits and structs
Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register
Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'include/linux/mlx5/driver.h')
| -rw-r--r-- | include/linux/mlx5/driver.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index d476255c9a3f..0c4f6acf59ca 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -100,6 +100,8 @@ enum { }; enum { + MLX5_REG_SBPR = 0xb001, + MLX5_REG_SBCM = 0xb002, MLX5_REG_QPTS = 0x4002, MLX5_REG_QETCR = 0x4005, MLX5_REG_QTCT = 0x400a, |