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authorAndrew Murray <andrew.murray@arm.com>2020-03-02 21:17:52 +0300
committerWill Deacon <will@kernel.org>2020-03-18 01:50:30 +0300
commit8673e02e58410e6c4cefa499efa846286e45a991 (patch)
tree60273aa60c2777d8a4dea7d56951f545731d2cfe /include/linux/perf
parentc854188ea01062f5a5fd7f05658feb1863774eaa (diff)
downloadlinux-8673e02e58410e6c4cefa499efa846286e45a991.tar.xz
arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
At present ARMv8 event counters are limited to 32-bits, though by using the CHAIN event it's possible to combine adjacent counters to achieve 64-bits. The perf config1:0 bit can be set to use such a configuration. With the introduction of ARMv8.5-PMU support, all event counters can now be used as 64-bit counters. Let's enable 64-bit event counters where support exists. Unless the user sets config1:0 we will adjust the counter value such that it overflows upon 32-bit overflow. This follows the same behaviour as the cycle counter which has always been (and remains) 64-bits. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Mark: fix ID field names, compare with 8.5 value] Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include/linux/perf')
-rw-r--r--include/linux/perf/arm_pmu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 71f525a35ac2..5b616dde9a4c 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -80,6 +80,7 @@ struct arm_pmu {
struct pmu pmu;
cpumask_t supported_cpus;
char *name;
+ int pmuver;
irqreturn_t (*handle_irq)(struct arm_pmu *pmu);
void (*enable)(struct perf_event *event);
void (*disable)(struct perf_event *event);