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authorAkash Asthana <akashast@codeaurora.org>2020-06-23 13:38:50 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-06-25 07:49:00 +0300
commit58ffbba6a39979baa22d2f7e69faeffa2d9c0641 (patch)
treea748e8a0a8329492ef8cbe1ae924962d900229d7 /include/linux/qcom-geni-se.h
parentbe24c6a71ecfbd9436ea1f496eb518a53e06368c (diff)
downloadlinux-58ffbba6a39979baa22d2f7e69faeffa2d9c0641.tar.xz
soc: qcom: geni: Support for ICC voting
Add necessary macros and structure variables to support ICC BW voting from individual SE drivers. Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1592908737-7068-2-git-send-email-akashast@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'include/linux/qcom-geni-se.h')
-rw-r--r--include/linux/qcom-geni-se.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index dd464943f717..80dbc01904d6 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -6,6 +6,8 @@
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
+#include <linux/interconnect.h>
+
/* Transfer mode supported by GENI Serial Engines */
enum geni_se_xfer_mode {
GENI_SE_INVALID,
@@ -25,6 +27,17 @@ enum geni_se_protocol_type {
struct geni_wrapper;
struct clk;
+enum geni_icc_path_index {
+ GENI_TO_CORE,
+ CPU_TO_GENI,
+ GENI_TO_DDR
+};
+
+struct geni_icc_path {
+ struct icc_path *path;
+ unsigned int avg_bw;
+};
+
/**
* struct geni_se - GENI Serial Engine
* @base: Base Address of the Serial Engine's register block
@@ -33,6 +46,7 @@ struct clk;
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
+ * @icc_paths: Array of ICC paths for SE
*/
struct geni_se {
void __iomem *base;
@@ -41,6 +55,7 @@ struct geni_se {
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
+ struct geni_icc_path icc_paths[3];
};
/* Common SE registers */
@@ -229,6 +244,21 @@ struct geni_se {
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
+/*
+ * Define bandwidth thresholds that cause the underlying Core 2X interconnect
+ * clock to run at the named frequency. These baseline values are recommended
+ * by the hardware team, and are not dynamically scaled with GENI bandwidth
+ * beyond basic on/off.
+ */
+#define CORE_2X_19_2_MHZ 960
+#define CORE_2X_50_MHZ 2500
+#define CORE_2X_100_MHZ 5000
+#define CORE_2X_150_MHZ 7500
+#define CORE_2X_200_MHZ 10000
+#define CORE_2X_236_MHZ 16383
+
+#define GENI_DEFAULT_BW Bps_to_icc(1000)
+
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
u32 geni_se_get_qup_hw_version(struct geni_se *se);
@@ -416,5 +446,13 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
+
+int geni_icc_get(struct geni_se *se, const char *icc_ddr);
+
+int geni_icc_set_bw(struct geni_se *se);
+
+int geni_icc_enable(struct geni_se *se);
+
+int geni_icc_disable(struct geni_se *se);
#endif
#endif