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authorLinus Torvalds <torvalds@linux-foundation.org>2023-02-26 02:16:23 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2023-02-26 02:16:23 +0300
commit1ec35eadc3b448c91a6b763371a7073444e95f9d (patch)
tree1a69e1cba5d832b4cb7745d043fcab8b47b9cd1e /include/linux
parent562ed38ded83a5cd3ecf9a1a875c7ee786c146ae (diff)
parentb64baafa24d2c430513329daf5ebb821620d0c03 (diff)
downloadlinux-1ec35eadc3b448c91a6b763371a7073444e95f9d.tar.xz
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "We have one small patch to the clk core this time around. It fixes a corner case with the CLK_OPS_PARENT_ENABLE flag combined with clk_core_is_enabled() where it hangs the system. We'll simply assume the clk is disabled if the parent is disabled and the flag is set. Trying to turn on the parent to check the enable state of the clk runs into system hangs at boot. We let this bake in -next for a couple weeks to make sure there aren't any more issues because the last attempt to fix this ran into hangs and had to be reverted. Note: There were some more patches to the core framework around sync_state and disabling unused clks, but I asked for that to be reverted from the qcom PR because it isn't ready and we're still discussing the best solution on the list. Outside of the core clk framework, we have the usual collection of clk driver updates and support for new SoCs (which seems to never stop). The dirstat is dominated by Qualcomm because they added support for quite a few SoCs this time around and also migrated quite a few of their drivers to clk_parent_data. The other big diff is in the Mediatek clk drivers that saw a significant rework this cycle to similarly modernize the code, and we'll see that work continue in the next cycle as well. Nothing really jumps out as scary here, except that the significant churn in parent data descriptions can have typos that go unnoticed. More details below. Core: - Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() New Drivers: - Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref clocks - Support for Mediatek MT7891 SoC clks - Support for many Qualcomm clk controllers: - QDU1000/QRU1000 global clock controller - SA8775P global clock controller - SM8550 TCSR and display clock controller - SM6350 clock controller - MSM8996 CBF and APCS clock controllers Updates: - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Versa 5P49V60 clks - Disable R-Car H3 ES1.*, as it was only available to an internal development group and needed a lot of quirks and workarounds - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and resets on Renesas RZ/V2M - Add display clocks on Renesas R-Car V4H - Add Camera Receiving Unit (CRU) clocks and resets on Renesas RZ/G2L - Free the imx_uart_clocks even if imx_register_uart_clocks returns early - Get the stdout clocks count from device tree on i.MX - Drop the clock count argument from imx_register_uart_clocks() - Keep the uart clocks on i.MX93 for when earlycon is used - Fix SPDX comment in i.MX6SLL clocks bindings header - Drop some unnecessary spaces from i.MX8ULP clocks bindings header - Add imx_obtain_fixed_of_clock() for allowing to add a clock that is not configured via devicetree - Fix the ENET1 gate configuration for i.MX6UL according to the reference manual - Add ENET refclock mux support for i.MX6UL - Add support for USB host/device configuration on Renesas RZ/N1 - Add PLL2 programming support, and CAN-FD clocks on Renesas R-Car V4H - Add D1 CAN bus gates and resets for Allwinner - Mark D1 CPUX clock as critical on Allwinner - Reuse D1 driver for Allwinner R528/T113 - Cleanup sunxi-ng Kconfig - Fix sunxi-ng kernel-doc issues - Model Allwinner H3/H5 DRAM clock as fixed clock - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll, sclk-div and cpu-dyn-div amlogic clock drivers - DDR clocks were marked as critical in the proper clock driver for each AT91 SoC such that drivers/memory/atmel-sdramc.c to be deleted in the next releases as it only does clock enablement - Patch to avoid compiling dt-compat.o for all AT91 SoCs as only some of them may use it - Support synchronous power_off requests in the qcom GDSC driver for proper GPU power collapse - Drop test clocks from various Qualcomm clk drivers - Update parent references to use clk_parent_data/clk_hw in various Qualcomm clk drivers - Fixes for the Qualcomm MSM8996 CPU clock controller - Transition Qualcomm MSM8974 GCC off the externally defined sleep_clk - Add GDSCs in the global clock controller for Qualcomm QCS404 - The SDCC core clocks on Qualcomm SM6115 are moved to floor_ops - Programming of clk_dis_wait for GPU CX GDSC on Qualcomm SC7180 and SDM845 are moved to use the recently introduced properties in the GDSC struct - Qualcomm's RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock is added on a variety of platforms - De-duplicate identical clks in Qualcomm SMD RPM clk driver - Add a few missing clocks across msm8998, msm8992, msm8916, qcs404 to Qualcomm SDM RPM clk driver - Various Qualcomm clk drivers use devm_pm_runtime_enable() to simplify" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (228 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused clk: imx: pll14xx: fix recalc_rate for negative kdiv clk: rs9: Drop unused pin_xin field MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function clk: mediatek: clk-mtk: Remove unneeded semicolon dt-bindings: clock: remove stih416 bindings dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file clk: imx: fix compile testing imxrt1050 clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h6
-rw-r--r--include/linux/pm_domain.h5
-rw-r--r--include/linux/soc/qcom/smd-rpm.h1
3 files changed, 9 insertions, 3 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d4b5e527a7a3..09c6b3184bb0 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -451,8 +451,10 @@
#define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0)
/* For imx6ul iomux gpr register field define */
-#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
-#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
+#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18)
+#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17)
+#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14)
+#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13)
#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17)
diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
index 1cd41bdf73cf..f776fb93eaa0 100644
--- a/include/linux/pm_domain.h
+++ b/include/linux/pm_domain.h
@@ -136,6 +136,7 @@ struct generic_pm_domain {
unsigned int prepared_count; /* Suspend counter of prepared devices */
unsigned int performance_state; /* Aggregated max performance state */
cpumask_var_t cpus; /* A cpumask of the attached CPUs */
+ bool synced_poweroff; /* A consumer needs a synced poweroff */
int (*power_off)(struct generic_pm_domain *domain);
int (*power_on)(struct generic_pm_domain *domain);
struct raw_notifier_head power_notifiers; /* Power on/off notifiers */
@@ -235,6 +236,7 @@ int dev_pm_genpd_add_notifier(struct device *dev, struct notifier_block *nb);
int dev_pm_genpd_remove_notifier(struct device *dev);
void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next);
ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev);
+void dev_pm_genpd_synced_poweroff(struct device *dev);
extern struct dev_power_governor simple_qos_governor;
extern struct dev_power_governor pm_domain_always_on_gov;
@@ -300,6 +302,9 @@ static inline ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev)
{
return KTIME_MAX;
}
+static inline void dev_pm_genpd_synced_poweroff(struct device *dev)
+{ }
+
#define simple_qos_governor (*(struct dev_power_governor *)(NULL))
#define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL))
#endif
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 62de54992e49..2990f425fdef 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -43,7 +43,6 @@ struct qcom_smd_rpm;
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
-#define QCOM_SMD_RPM_MMXI_CLK 0x69786d6d
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,