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authorClaudiu Beznea <claudiu.beznea@microchip.com>2022-01-13 17:48:53 +0300
committerNicolas Ferre <nicolas.ferre@microchip.com>2022-02-25 14:36:25 +0300
commit9a0775c9cd3d89d1fe957a137131681a33f5736b (patch)
tree562eec472c45cf21354d65e07e41fcfeaf9088bd /include/soc/at91
parent55614e682a2c9fac12a0f121b43b93ff4915d0e6 (diff)
downloadlinux-9a0775c9cd3d89d1fe957a137131681a33f5736b.tar.xz
ARM: at91: ddr: fix typo to align with datasheet naming
Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet naming. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
Diffstat (limited to 'include/soc/at91')
-rw-r--r--include/soc/at91/sama7-ddr.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 817b360efbb8..fee1b11bddca 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -53,7 +53,7 @@
#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */
#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
-#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */
+#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */