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authorPetlozu Pravareshwar <petlozup@nvidia.com>2022-09-30 19:02:13 +0300
committerThierry Reding <treding@nvidia.com>2022-11-10 04:21:12 +0300
commitc9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3 (patch)
tree70091959ae43d4537e659ef4807e4b5d75306912 /include/soc/tegra
parentcc5b2ad5393ec237c8697bb3989a34c0c3beb2f6 (diff)
downloadlinux-c9c4ddb20c427b19c6a2a1787bf82c7b2aac25c3.tar.xz
soc/tegra: pmc: Add I/O pad table for Tegra234
Add I/O pad table for Tegra234 to allow configuring DPD mode and switching the pins to 1.8V or 3.3V as needed. On Tegra234, DPD registers are reorganized such that there is a DPD_REQ register and a DPD_STATUS register per pad group. Update the PMC driver accordingly. While at it, use the generated tables from tegra-pinmux-scripts to make the formatting of these tables more consistent. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> [treding@nvidia.com: generate tables from tegra-pinmux-scripts] Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc/tegra')
-rw-r--r--include/soc/tegra/pmc.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index d186bccd125d..aadb845d281d 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -118,9 +118,9 @@ enum tegra_io_pad {
TEGRA_IO_PAD_PEX_CLK_2,
TEGRA_IO_PAD_PEX_CNTRL,
TEGRA_IO_PAD_PEX_CTL2,
- TEGRA_IO_PAD_PEX_L0_RST_N,
- TEGRA_IO_PAD_PEX_L1_RST_N,
- TEGRA_IO_PAD_PEX_L5_RST_N,
+ TEGRA_IO_PAD_PEX_L0_RST,
+ TEGRA_IO_PAD_PEX_L1_RST,
+ TEGRA_IO_PAD_PEX_L5_RST,
TEGRA_IO_PAD_PWR_CTL,
TEGRA_IO_PAD_SDMMC1,
TEGRA_IO_PAD_SDMMC1_HV,