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authorHolger Brunck <holger.brunck@keymile.com>2017-05-17 18:24:38 +0300
committerDavid S. Miller <davem@davemloft.net>2017-05-18 17:28:39 +0300
commit067bb938dad61e58fc3d6a0e090b72ec011851cd (patch)
tree617e9b79f94dfe0cdff171fae024b7f13353b657 /include/soc
parentc7f235a7c2d09b1b83671ba2d93ebee981554467 (diff)
downloadlinux-067bb938dad61e58fc3d6a0e090b72ec011851cd.tar.xz
net/wan/fsl_ucc_hdlc: add hdlc-bus support
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/fsl/qe/qe.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 226f915a68c2..b3d1aff5e8ad 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -789,6 +789,11 @@ struct ucc_slow_pram {
#define UCC_GETH_UPSMR_SMM 0x00000080
#define UCC_GETH_UPSMR_SGMM 0x00000020
+/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
+#define UCC_HDLC_UPSMR_RTE 0x02000000
+#define UCC_HDLC_UPSMR_BUS 0x00200000
+#define UCC_HDLC_UPSMR_CW8 0x00007000
+
/* UCC Transmit On Demand Register (UTODR) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000