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authorLinus Torvalds <torvalds@linux-foundation.org>2023-02-25 20:19:23 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2023-02-25 20:19:23 +0300
commit7c3dc440b1f5c75f45e24430f913e561dc82a419 (patch)
tree7c3e037691d712a20f7e95279cc1e090328d5d44 /include/trace
parentd8e473182ab9e85708067be81d20424045d939fa (diff)
parente686c32590f40bffc45f105c04c836ffad3e531a (diff)
downloadlinux-7c3dc440b1f5c75f45e24430f913e561dc82a419.tar.xz
Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
Pull Compute Express Link (CXL) updates from Dan Williams: "To date Linux has been dependent on platform-firmware to map CXL RAM regions and handle events / errors from devices. With this update we can now parse / update the CXL memory layout, and report events / errors from devices. This is a precursor for the CXL subsystem to handle the end-to-end "RAS" flow for CXL memory. i.e. the flow that for DDR-attached-DRAM is handled by the EDAC driver where it maps system physical address events to a field-replaceable-unit (FRU / endpoint device). In general, CXL has the potential to standardize what has historically been a pile of memory-controller-specific error handling logic. Another change of note is the default policy for handling RAM-backed device-dax instances. Previously the default access mode was "device", mmap(2) a device special file to access memory. The new default is "kmem" where the address range is assigned to the core-mm via add_memory_driver_managed(). This saves typical users from wondering why their platform memory is not visible via free(1) and stuck behind a device-file. At the same time it allows expert users to deploy policy to, for example, get dedicated access to high performance memory, or hide low performance memory from general purpose kernel allocations. This affects not only CXL, but also systems with high-bandwidth-memory that platform-firmware tags with the EFI_MEMORY_SP (special purpose) designation. Summary: - CXL RAM region enumeration: instantiate 'struct cxl_region' objects for platform firmware created memory regions - CXL RAM region provisioning: complement the existing PMEM region creation support with RAM region support - "Soft Reservation" policy change: Online (memory hot-add) soft-reserved memory (EFI_MEMORY_SP) by default, but still allow for setting aside such memory for dedicated access via device-dax. - CXL Events and Interrupts: Takeover CXL event handling from platform-firmware (ACPI calls this CXL Memory Error Reporting) and export CXL Events via Linux Trace Events. - Convey CXL _OSC results to drivers: Similar to PCI, let the CXL subsystem interrogate the result of CXL _OSC negotiation. - Emulate CXL DVSEC Range Registers as "decoders": Allow for first-generation devices that pre-date the definition of the CXL HDM Decoder Capability to translate the CXL DVSEC Range Registers into 'struct cxl_decoder' objects. - Set timestamp: Per spec, set the device timestamp in case of hotplug, or if platform-firwmare failed to set it. - General fixups: linux-next build issues, non-urgent fixes for pre-production hardware, unit test fixes, spelling and debug message improvements" * tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (66 commits) dax/kmem: Fix leak of memory-hotplug resources cxl/mem: Add kdoc param for event log driver state cxl/trace: Add serial number to trace points cxl/trace: Add host output to trace points cxl/trace: Standardize device information output cxl/pci: Remove locked check for dvsec_range_allowed() cxl/hdm: Add emulation when HDM decoders are not committed cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decoders cxl/hdm: Emulate HDM decoder from DVSEC range registers cxl/pci: Refactor cxl_hdm_decode_init() cxl/port: Export cxl_dvsec_rr_decode() to cxl_port cxl/pci: Break out range register decoding from cxl_hdm_decode_init() cxl: add RAS status unmasking for CXL cxl: remove unnecessary calling of pci_enable_pcie_error_reporting() dax/hmem: build hmem device support as module if possible dax: cxl: add CXL_REGION dependency cxl: avoid returning uninitialized error code cxl/pmem: Fix nvdimm registration races cxl/mem: Fix UAPI command comment cxl/uapi: Tag commands from cxl_query_cmd() ...
Diffstat (limited to 'include/trace')
-rw-r--r--include/trace/events/cxl.h112
1 files changed, 0 insertions, 112 deletions
diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
deleted file mode 100644
index ad085a2534ef..000000000000
--- a/include/trace/events/cxl.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM cxl
-
-#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _CXL_EVENTS_H
-
-#include <linux/tracepoint.h>
-
-#define CXL_HEADERLOG_SIZE SZ_512
-#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
-
-#define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0)
-#define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1)
-#define CXL_RAS_UC_CACHE_BE_PARITY BIT(2)
-#define CXL_RAS_UC_CACHE_DATA_ECC BIT(3)
-#define CXL_RAS_UC_MEM_DATA_PARITY BIT(4)
-#define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5)
-#define CXL_RAS_UC_MEM_BE_PARITY BIT(6)
-#define CXL_RAS_UC_MEM_DATA_ECC BIT(7)
-#define CXL_RAS_UC_REINIT_THRESH BIT(8)
-#define CXL_RAS_UC_RSVD_ENCODE BIT(9)
-#define CXL_RAS_UC_POISON BIT(10)
-#define CXL_RAS_UC_RECV_OVERFLOW BIT(11)
-#define CXL_RAS_UC_INTERNAL_ERR BIT(14)
-#define CXL_RAS_UC_IDE_TX_ERR BIT(15)
-#define CXL_RAS_UC_IDE_RX_ERR BIT(16)
-
-#define show_uc_errs(status) __print_flags(status, " | ", \
- { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \
- { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \
- { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \
- { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \
- { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \
- { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \
- { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \
- { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \
- { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \
- { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \
- { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \
- { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \
- { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \
- { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \
- { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
-)
-
-TRACE_EVENT(cxl_aer_uncorrectable_error,
- TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
- TP_ARGS(dev, status, fe, hl),
- TP_STRUCT__entry(
- __string(dev_name, dev_name(dev))
- __field(u32, status)
- __field(u32, first_error)
- __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
- ),
- TP_fast_assign(
- __assign_str(dev_name, dev_name(dev));
- __entry->status = status;
- __entry->first_error = fe;
- /*
- * Embed the 512B headerlog data for user app retrieval and
- * parsing, but no need to print this in the trace buffer.
- */
- memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
- ),
- TP_printk("%s: status: '%s' first_error: '%s'",
- __get_str(dev_name),
- show_uc_errs(__entry->status),
- show_uc_errs(__entry->first_error)
- )
-);
-
-#define CXL_RAS_CE_CACHE_DATA_ECC BIT(0)
-#define CXL_RAS_CE_MEM_DATA_ECC BIT(1)
-#define CXL_RAS_CE_CRC_THRESH BIT(2)
-#define CLX_RAS_CE_RETRY_THRESH BIT(3)
-#define CXL_RAS_CE_CACHE_POISON BIT(4)
-#define CXL_RAS_CE_MEM_POISON BIT(5)
-#define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6)
-
-#define show_ce_errs(status) __print_flags(status, " | ", \
- { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \
- { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \
- { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \
- { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \
- { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \
- { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \
- { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \
-)
-
-TRACE_EVENT(cxl_aer_correctable_error,
- TP_PROTO(const struct device *dev, u32 status),
- TP_ARGS(dev, status),
- TP_STRUCT__entry(
- __string(dev_name, dev_name(dev))
- __field(u32, status)
- ),
- TP_fast_assign(
- __assign_str(dev_name, dev_name(dev));
- __entry->status = status;
- ),
- TP_printk("%s: status: '%s'",
- __get_str(dev_name), show_ce_errs(__entry->status)
- )
-);
-
-#endif /* _CXL_EVENTS_H */
-
-/* This part must be outside protection */
-#undef TRACE_INCLUDE_FILE
-#define TRACE_INCLUDE_FILE cxl
-#include <trace/define_trace.h>