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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2023-02-11 10:41:09 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-02-13 14:12:31 +0300 |
| commit | 022c3f87f88e2d68e90be7687d981c9cb893a3b1 (patch) | |
| tree | fc262dd87f60a5a73f44c535fcb49ff7ca67bb53 /include/uapi/linux/mdio.h | |
| parent | cf9f6079696840093aa6ea3c0ee405a553afe2fb (diff) | |
| download | linux-022c3f87f88e2d68e90be7687d981c9cb893a3b1.tar.xz | |
net: phy: add genphy_c45_ethtool_get/set_eee() support
Add replacement for phy_ethtool_get/set_eee() functions.
Current phy_ethtool_get/set_eee() implementation is great and it is
possible to make it even better:
- this functionality is for devices implementing parts of IEEE 802.3
specification beyond Clause 22. The better place for this code is
phy-c45.c
- currently it is able to do read/write operations on PHYs with
different abilities to not existing registers. It is better to
use stored supported_eee abilities to avoid false read/write
operations.
- the eee_active detection will provide wrong results on not supported
link modes. It is better to validate speed/duplex properties against
supported EEE link modes.
- it is able to support only limited amount of link modes. We have more
EEE link modes...
By refactoring this code I address most of this point except of the last
one. Adding additional EEE link modes will need more work.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/uapi/linux/mdio.h')
| -rw-r--r-- | include/uapi/linux/mdio.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index 75b7257a51e1..256b463e47a6 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -79,6 +79,8 @@ #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */ #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */ #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */ +#define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */ +#define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */ #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */ /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ @@ -340,6 +342,12 @@ #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */ #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */ +/* 10BASE-T1 AN control register */ +#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */ + +/* 10BASE-T1 AN status register */ +#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */ + /* BASE-T1 PMA/PMD control register */ #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */ |