diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2023-02-14 20:00:24 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-02-15 01:12:54 +0300 |
| commit | 248529edc86f8d7d390a15a86bd1904951311665 (patch) | |
| tree | 0eb11c11d179bca096a9c8539a3dd02bbe39c1d3 /include/uapi/linux/pci_regs.h | |
| parent | 1922a6dc0502ed3fd0786f57cc9e5f515c902009 (diff) | |
| download | linux-248529edc86f8d7d390a15a86bd1904951311665.tar.xz | |
cxl: add RAS status unmasking for CXL
By default the CXL RAS mask registers bits are defaulted to 1's and
suppress all error reporting. If the kernel has negotiated ownership
of error handling for CXL then unmask the mask registers by writing 0s.
PCI_EXP_DEVCTL capability is checked to see uncorrectable or correctable
errors bits are set before unmasking the respective errors.
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_regs.h
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/167639402301.778884.12556849214955646539.stgit@djiang5-mobl3.local
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 85ab1278811e..dc2000e0fe3a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -693,6 +693,7 @@ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ +#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ |