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authorDavid Lechner <david@lechnology.com>2017-01-05 21:54:18 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-12 13:51:25 +0300
commita2d6a987bfe4a2e344fae9d255200072eb082427 (patch)
tree1c359520dd331f98d68a4e8bf329eebd2a935805 /include/uapi/linux/serial_reg.h
parentb2ae93e0580c8d08c6a84e9188068c0e74930112 (diff)
downloadlinux-a2d6a987bfe4a2e344fae9d255200072eb082427.tar.xz
serial: 8250: Add new port type for TI DA8xx/66AK2x
This adds a new UART port type for TI DA8xx/OMAPL13x/AM17xx/AM18xx/66AK2x. These SoCs have standard 8250 registers plus some extra non-standard registers. The UART will not function unless the non-standard Power and Emulation Management Register (PWREMU_MGMT) is configured correctly. This is currently handled in arch/arm/mach-davinci/serial.c for non-device-tree boards. Making this part of the UART driver will allow UART to work on device-tree boards as well and the mach code can eventually be removed. Signed-off-by: David Lechner <david@lechnology.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/serial_reg.h')
-rw-r--r--include/uapi/linux/serial_reg.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index b4c04842a8c0..274d8fc206e3 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -327,6 +327,14 @@
#define SERIAL_RSA_BAUD_BASE (921600)
#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
+/* Extra registers for TI DA8xx/66AK2x */
+#define UART_DA830_PWREMU_MGMT 12
+
+/* PWREMU_MGMT register bits */
+#define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
+#define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */
+#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */
+
/*
* Extra serial register definitions for the internal UARTs
* in TI OMAP processors.