summaryrefslogtreecommitdiff
path: root/include/uapi/linux/v4l2-dv-timings.h
diff options
context:
space:
mode:
authorHans Verkuil <hans.verkuil@cisco.com>2013-03-20 21:31:34 +0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2013-04-15 02:56:36 +0400
commita7b74bd82a26379495e0e727d2c0fa9b0b97d917 (patch)
treee73d7a6aaa6f8a7dbdbdd152344edc9018b278cf /include/uapi/linux/v4l2-dv-timings.h
parent292a878720b26213bc773619715525e9f7a4f4a1 (diff)
downloadlinux-a7b74bd82a26379495e0e727d2c0fa9b0b97d917.tar.xz
[media] v4l2-dv-timings.h: add 480i59.94 and 576i50 CEA-861-E timings
These formats are supported by the HDPVR, but they were missing in the list. Note that these formats are different from the common PAL/NTSC/SECAM formats since all color channels are transmitted separately and so there is no PAL or NTSC or SECAM color encoding involved. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/uapi/linux/v4l2-dv-timings.h')
-rw-r--r--include/uapi/linux/v4l2-dv-timings.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h
index 9ef8172e5ed0..4e0c58d25ff0 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -42,6 +42,15 @@
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
}
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements. */
+#define V4L2_DV_BT_CEA_720X480I59_94 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
+ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
+}
+
#define V4L2_DV_BT_CEA_720X480P59_94 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
@@ -49,6 +58,15 @@
V4L2_DV_BT_STD_CEA861, 0) \
}
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements. */
+#define V4L2_DV_BT_CEA_720X576I50 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
+ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
+}
+
#define V4L2_DV_BT_CEA_720X576P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \