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authorLinus Torvalds <torvalds@linux-foundation.org>2023-02-26 02:05:08 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2023-02-26 02:05:08 +0300
commit2e3036a2642b6145a8117d21514bfc5f8d5ea595 (patch)
tree69aa0a5eb1bbf8113bdbd2257dda1d5476318b92 /include
parent60e2bf7d10e9cd5641f4a5183a19058d9a2c8782 (diff)
parentf4440abc08917d9a7032abb8a6a5d4b36ca979b6 (diff)
downloadlinux-2e3036a2642b6145a8117d21514bfc5f8d5ea595.tar.xz
Merge tag 'mtd/for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal: "MTD changes: - parsers: ofpart: add workaround for #size-cells 0 - dt-bindings: partitions: Fix partition node name pattern - dataflash: remove duplicate SPI ID table Raw NAND core changes: - Check the data only read pattern only once - Prepare the late addition of supported operation checks - Support for sequential cache reads - Fix nand_chip kdoc Raw NAND driver changes: - Fsl_elbc: Propagate HW ECC settings to HW - Marvell: Add missing layouts - Pasemi: Don't use static data to track per-device state - Sunxi: - Fix the size of the last OOB region - Remove an unnecessary check - Remove an unnecessary check - Clean up chips after failed init - Precompute the ECC_CTL register value - Embed sunxi_nand_hw_ecc by value - Update OOB layout to match hardware - tmio_nand: Remove driver - vf610_nfc: Use regular comments for functions SPI-NAND driver changes: - Add support for AllianceMemory AS5F34G04SND - Macronix: use scratch buffer for DMA operation NAND ECC changes: - Mediatek: - Add ECC support fot MT7986 IC - Add compatible for MT7986 - dt-bindings: Split ECC engine with rawnand controller SPI NOR changes: - Misc core fixes SPI NOR driver changes: - Spansion: Minor fixes" * tag 'mtd/for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (33 commits) mtd: parsers: ofpart: add workaround for #size-cells 0 mtd: rawnand: sunxi: Precompute the ECC_CTL register value mtd: rawnand: sunxi: Embed sunxi_nand_hw_ecc by value mtd: rawnand: sunxi: Update OOB layout to match hardware mtd: spi-nor: Sort headers alphabetically mtd: spi-nor: Fix shift-out-of-bounds in spi_nor_set_erase_type mtd: nand: ecc-mtk: Add ECC support fot MT7986 IC dt-bindings: mtd: mediatek,nand-ecc-engine: Add compatible for MT7986 dt-bindings: mtd: Split ECC engine with rawnand controller mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW mtd: spinand: Add support for AllianceMemory AS5F34G04SND dt-bindings: mtd: partitions: Fix partition node name pattern mtd: spi-nor: Create macros to define chip IDs and geometries mtd: spi-nor: spansion: Make CFRx reg fields generic mtd: spi-nor: spansion: Consider reserved bits in CFR5 register mtd: spi-nor: core: fix implicit declaration warning mtd: spinand: macronix: use scratch buffer for DMA operation mtd: rawnand: Fix nand_chip kdoc mtd: rawnand: vf610_nfc: use regular comments for functions mtd: rawnand: Support for sequential cache reads ...
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/rawnand.h21
-rw-r--r--include/linux/mtd/spinand.h1
2 files changed, 22 insertions, 0 deletions
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index dcf90144d70b..f8d4be9c587a 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -67,6 +67,8 @@ struct gpio_desc;
/* Extended commands for large page devices */
#define NAND_CMD_READSTART 0x30
+#define NAND_CMD_READCACHESEQ 0x31
+#define NAND_CMD_READCACHEEND 0x3f
#define NAND_CMD_RNDOUTSTART 0xE0
#define NAND_CMD_CACHEDPROG 0x15
@@ -1094,10 +1096,20 @@ struct nand_controller_ops {
*
* @lock: lock used to serialize accesses to the NAND controller
* @ops: NAND controller operations.
+ * @supported_op: NAND controller known-to-be-supported operations,
+ * only writable by the core after initial checking.
+ * @supported_op.data_only_read: The controller supports reading more data from
+ * the bus without restarting an entire read operation nor
+ * changing the column.
+ * @supported_op.cont_read: The controller supports sequential cache reads.
*/
struct nand_controller {
struct mutex lock;
const struct nand_controller_ops *ops;
+ struct {
+ unsigned int data_only_read: 1;
+ unsigned int cont_read: 1;
+ } supported_op;
};
static inline void nand_controller_init(struct nand_controller *nfc)
@@ -1248,6 +1260,10 @@ struct nand_secure_region {
* @read_retries: The number of read retry modes supported
* @secure_regions: Structure containing the secure regions info
* @nr_secure_regions: Number of secure regions
+ * @cont_read: Sequential page read internals
+ * @cont_read.ongoing: Whether a continuous read is ongoing or not
+ * @cont_read.first_page: Start of the continuous read operation
+ * @cont_read.last_page: End of the continuous read operation
* @controller: The hardware controller structure which is shared among multiple
* independent devices
* @ecc: The ECC controller structure
@@ -1300,6 +1316,11 @@ struct nand_chip {
int read_retries;
struct nand_secure_region *secure_regions;
u8 nr_secure_regions;
+ struct {
+ bool ongoing;
+ unsigned int first_page;
+ unsigned int last_page;
+ } cont_read;
/* Externals */
struct nand_controller *controller;
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 6d3392a7edc6..01be9f0f008a 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -260,6 +260,7 @@ struct spinand_manufacturer {
};
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
extern const struct spinand_manufacturer ato_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;